XIO2001_101 Datasheet, PDF (112/131 Pages) Texas Instruments – PCI Express™ to PCI Bus Translation Bridge

XIO2001
SCPS212D – MAY 2009 – REVISED JANUARY 2010
Table 6-8. Serial IRQ Status Register Description (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
0⁽¹⁾ IRQ0
RCU
IRQ 0 asserted. This bit indicates that the IRQ0 has been asserted.
0 = Deasserted
1 = Asserted
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6.12 Pre-Fetch Agent Request Limits Register
This register is used to set the Pre-Fetch Agent's limits on retrieving data using upstream reads. This
register is an alias for the pre-fetch agent request limits register in the classic PCI configuration space
(offset E8h, see Section 4.75). See Table 6-9 for a complete description of the register contents.
Device control memory window
register offset:
Register type:
Default value:
50h
Read/Clear
0443h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
Table 6-9. Pre-Fetch Agent Request Limits Register Description
BIT
FIELD NAME
15:12 RSVD
ACCESS
DESCRIPTION
R
Reserved. Returns 0h when read.
11:8 ⁽¹⁾
PFA_REQ_
CNT_LIMIT
Request count limit. Determines the number of Pre-Fetch reads that takes place in each
burst.
RW
4'h0 = Auto-prefetch agent is disabled.
4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated.
4'h2:F = Thread will be limited to initial read and (PFA_REQ_CNT_LIMIT – 1)
Completion cache mode. Determines the rules for completing the caching process.
00 = No caching.
• Pre-fetching is disabled.
• All remaining read completion data will be discarded after any of the data has been
returned to the PCI master.
01 = Light caching.
• Pre-fetching is enabled.
• All remaining read completion data will be discarded after data has been returned to
7:6
PFA_CPL_CACHE_
MODE
RW
the PCI master and the PCI master terminated the transfer.
• All remaining read completion data will be cached after data has been returned to the
PCI master and the bridge has terminated the transfer with RETRY.
10 = Full caching.
• Pre-fetching is enabled.
• All remaining read completion data will be cached after data has been returned to the
PCI master and the PCI master terminated the transfer.
• All remaining read completion data will be cached after data has been returned to the
PCI master and the bridge has terminated the transfer with RETRY.
5:4 RSVD
11 = Reserved.
R
Reserved. Returns 00b when read.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
112 Memory-Mapped TI Proprietary Register Space
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