XIO2001_101 Datasheet, PDF (50/131 Pages) Texas Instruments – PCI Express™ to PCI Bus Translation Bridge

XIO2001
SCPS212D – MAY 2009 – REVISED JANUARY 2010
www.ti.com
4.17 Secondary Status Register
The secondary status register provides information about the PCI bus interface. See Table 4-8 for a
complete description of the register contents.
PCI register offset:
Register type:
1Eh
Read-only, Read/Clear
Default value:
02X0h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
BIT FIELD NAME
15 PAR_ERR
14 SYS_ERR
13 MABORT
12 TABORT_REC
11 TABORT_SIG
10:9 PCI_SPEED
8 DATAPAR
7 FBB_CAP
6 RSVD
5 66MHZ
4:0 RSVD
Table 4-8. Secondary Status Register Description
ACCESS
RCU
RCU
RCU
RCU
RCU
R
RCU
R
R
R
R
DESCRIPTION
Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data
error by the bridge on its internal PCI bus secondary interface. This bit must be set when any of the
following three conditions are true:
• The bridge detects an uncorrectable address or attribute error as a potential target.
• The bridge detects an uncorrectable data error when it is the target of a write transaction.
• The bridge detects an uncorrectable data error when it is the master of a read transaction
(immediate read data).
The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh
(see Section 4.29).
0 = Uncorrectable address, attribute, or data error not detected on secondary interface
1 = Uncorrectable address, attribute, or data error detected on secondary interface
Received system error. This bit is set when the bridge detects an SERR assertion.
0 = No error asserted on the PCI interface
1 = SERR asserted on the PCI interface
Received master abort. This bit is set when the PCI interface of the bridge reports the detection of a
master abort termination by the bridge when it is the master of a transaction on its secondary
interface.
0 = Master abort not received on the PCI interface
1 = Master abort received on the PCI interface
Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.
0 = Target abort not received on the PCI interface
1 = Target abort received on the PCI interface
Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when it
responds as the target of a transaction on its secondary interface.
0 = Target abort not signaled on the PCI interface
1 = Target abort signaled on the PCI interface
DEVSEL timing. These bits are 01b indicating that this is a medium speed decoding device.
Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI
bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.29) is set, and the
bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.
0 = No data parity error detected on the PCI interface
1 = Data parity error detected on the PCI Interface
Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI
interface of bridge supports fast back-to-back transactions.
Reserved. Returns 0b when read.
66-MHz capable. The bridge operates at a PCI bus CLK frequency of 66 MHz; therefore, this bit
always returns a 1b.
Reserved. Returns 00000b when read.
50
Classic PCI Configuration Space
Submit Documentation Feedback
Product Folder Link(s): XIO2001
Copyright © 2009–2010, Texas Instruments Incorporated