TLC5910 Datasheet, PDF (7/30 Pages) Texas Instruments – LED DRIVER

TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
Terminal Functions (Continued)
TERMINAL
NAME
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{OUT0–DOUT15}
2,3,5,6,8,9,11,12,
14,15,17,18,20,21,
23,24
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _PDOUT
70
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RBIAS
74
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RSEL0
60
RSEL1
59
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{TEST1–TEST4}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{THERMAL PAD}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _TSENA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCOIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCANA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCLOG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCIF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VCCLED
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _WDTRG
29,97,99,100
package bottom
31
75
33
93
92
26
56
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _WDCAP
30
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XDCLAT
61
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XDOWN1
55
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XDOWN2
54
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XDWN2TST
27
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XENABLE
66
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XGSOUT
52
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XLATCH
63
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XOE
65
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XPOUT
51
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XRST
34
I/O
DESCRIPTION
O Constant current output
I/O Resistor connection for PLL feedback adjustment
I/O Resistor connection for PLL oscillation frequency setting
Input/output port selection and shift register data latch switching.
When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected
to port A and the dot correction register latch is selected to port B.
I When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to
port A and the dot correction register latch is selected to port B.
When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port
A and no register latch is selected to port B.
I TEST. Factory test terminal. These terminals should be connected to GND.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
I
TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is
low, TSD is disabled.
I/O Capacitance connection for PLL feedback adjustment
Analog power supply voltage
Logic power supply voltage
Interface power supply voltage
LED driver power supply voltage
WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan
I signal can be monitored by turning the constant current output off and protecting the LED
from damage when the scan signal stopped during the constant period designed.
WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor
I/O between WDCAP and GND. When WDCAP is directly connected to GND, WDT function
is disabled. In this case, WDTRG should be tied to a high or low level.
Data latch for dot correction. When XDCLAT is high, data on the shift register for dot
I
correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is
latched. Accordingly, if data on the shift register is changed during XDCLAT high, this new
value is latched (level latch).
Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current
O _{output is shut down by WDT or TSD function.}
O
LED disconnection detection output. XDOWN2 is configured as an open collector.
XDOWN2 goes low when an LED disconnection is detected.
I
Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally
pulled up with 50 kΩ)
I
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.
O
Clock output for gray scale. When MAG0 to MAG2 are all low, the clock with GSCLK inverted
appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal.
Latch. When XLATCH is high, data on the shift register from DIN (port A) goes through latch.
I When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed
during XLATCH high, this new value is latched (level latch).
I
Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,
DOUT0–9 terminals go to a high-impedance state.
O GSPOL output inverted
I
Blank (Light off). When XRST is low, all the output of the constant current driver is turned
off. (This terminal is internally pulled up with 50 kΩ)
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