TLC5910 Datasheet, PDF (13/30 Pages) Texas Instruments – LED DRIVER

PRINCIPLES OF OPERATION
TLC5910
LED DRIVER
SLLS392 – NOVEMBER 1999
setting for output constant current value
On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through
external resistor, R_IREF (connected between IREF and GND), can flow. The external resistor value is calculated
using the following equation:
R_IREF (Ω) ≅ 38 × 1.21 (V)/I_O(LC)(A) where both BCENA and DCENA are low.
Note that more current flows if IREF is connected to GND directly.
constant output current operation
If GSPOL is high, the constant current output turns on the sink constant current if all the gray scale data in the
gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale
clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10 bit gray
scale counter. Then, the output counted corresponding to the gray scale data is turned off (stop to sink constant
current). The gray scale clock can be selected from GSCLK or that generated by internal PLL circuitry. If the
shift register for gray scale is updated during XLATCH high, data on the gray scale data latch is also updated
affecting the constant current output number of the gray scale. Accordingly, during the on-state of the constant
current output, keep the XLATCH to a low level and hold the gray scale data latch.
input/output port and shift register selection
The TLC5910 supplies two parallel input ports such as DIN (10 bits) and DCDIN (6 bits). The DIN and DCDIN
ports also supply DCLK and DCCLK for shift clock, XLATCH and XDCLAT for latch, and DOUT and DCDOUT
for output, respectively. The device has three types of shift register latches, gray scale data, brightness control,
and dot correction. The port and shift register can be selected by RSEL0 and RSEL1. Table 1 shows the
selection using RESL0 and RSEL1. Note that the RSELn setting should be done at DCLK low, (when DPOL
is high, and at DCLK high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and
XDCLAT should be connected to GND.
Table 1. Shift Register Latch Selection
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SELECTED SHIFT REGISTER LATCH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PORT A
RSEL1 RSEL0
DIN, DCLK, XLATCH, DOUT
PORT B
DCDIN, DCCLK, XDCLATCH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _L
L
Gray scale data displayed
Dot correction
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _L
H
Brightness control
Dot correction
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _H
L
Dot correction (see Note)
Not connected
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _H
H
N/A (inhibit)
N/A (inhibit)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{NOTE: Zero is output to DOUT6 to DOUT9.}
DCDOUT
Dot correction
Dot correction
Dot correction
N/A (inhibit)
shift register latch for gray scale data
The shift register latch for gray scale data is configured with 16 x 10 bits. The gray scale data, configured with
10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023
(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). When
the gray scale data is 1023, the time is longest, and it turns on during time of 1023 clocks from the gray scale
clock. The configuration of the shift register and latch for gray scale data is shown in Figure 3.
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