TLC5618 Datasheet, PDF (7/26 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
operating characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted) (continued)
digital input timing requirements
tsu(DS)
th(DH)
tsu(CSS)
tsu(CS1)
tsu(CS2)
tw(CL)
tw(CH)
td(CS1)
Setup time, DIN before SCLK low
Hold time, DIN valid after SCLK low
Setup time, CS low to SCLK low
Setup time, SCLK ↓ to CS ↑, external end-of-write
Setup time, SCLK ↑ to CS ↓, start of next write cycle
Pulse duration, SCLK low
Pulse duration, SCLK high
Delay time, CLK↑ to data disable (TLC5618A only)
MIN NOM MAX UNIT
5
ns
5
ns
5
ns
10
ns
5
ns
25
ns
25
ns
5
20 ns
CS
tsu(CSS)
tw(CL)
tw(CH)
tsu(CS1)
tsu(CS2)
SCLK
(see Note A)
tsu(DS)
ÎÎÎÎÎÎÎÎÎ _DIN
D15
DAC A/B
OUT
th(DH)
D14
D13
ÏÏÏÏÏÏ ^{Program Bits (4)}
D12 _ÏÏÏD_ÏÏÏ1DB1Ait_{ÏÏÏCsDD(1a0ÏÏÏ2t)a} ^{ÎÎÎÏÏÏÎÎÎÎÎÎÏÎÎÎÏÎÎÎ}_{tsÏÎÎÎÎÎÎ}
≤ Final Value ±0.5 LSB
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
Figure 1. Timing Diagram for the TLC5618
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