TLC5618 Datasheet, PDF (6/26 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted) (continued)
reference input (REFIN)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VI Input voltage range
Ri Input resistance
Ci Input capacitance
Reference feedthrough
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9)
0
VDD– 2 V
10
MΩ
5
pF
– 60
dB
Reference input bandwidth (f – 3 dB) REFIN = 0.2 Vpp + 1.024 V dc
Slow
Fast
0.5
MHz
1
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFIN) input = 1.024 V dc + 1 Vpp
at 1 kHz.
digital inputs (DIN, SCLK, CS)
PARAMETER
IIH High-level digital input current
IIL
Low-level digital input current
Ci
Input capacitance
TEST CONDITIONS
VI = VDD
VI = 0 V
MIN TYP MAX UNIT
± 1 µA
± 1 µA
8
pF
power supply
PARAMETER
IDD Power supply current
Power down supply current
TEST CONDITIONS
VDD = 5.5 V,
No load,
All inputs = 0 V or VDD
D13 = 0 (see Table 2)
Slow
Fast
MIN TYP MAX UNIT
0.6
1
mA
1.6 2.5
1
µA
operating characteristics over recommended operating free-air temperature range, V_DD = 5 V ± 5%,
V_ref(REFIN) = 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SR+
Output slew rate, positive
SR–
Output slew rate, negative
ts
Output settling time
ts(c)
Output settling time,
code-to-code
CL = 100 pF,
Vref(REFIN) = 2.048 V, _Slow
0.3
0.5
RL = 10 kΩ,
TA = 25°C,
Code 32 to Code 4096, VO from 10% to 90% ^Fast
2.4
3
CL = 100 pF,
Vref(REFIN) = 2.048 V, _{Slow 0.15 0.25}
RL = 10 kΩ,
TA = 25°C,
Code 4096 to Code 32, VO from 10% to 90% ^Fast
1.2 1.5
To ± 0.5 LSB,
RL = 10 kΩ,
CL = 100 pF,
See Note 10
Slow
12.5
Fast
2.5
To ± 0.5 LSB,
CL = 100 pF,
Slow
2
RL = 10 kΩ,
See Note 11
Fast
2
V/µs
V/µs
µs
µs
Glitch energy
S/(N+D) Signal to noise + distortion
DIN = All 0s to all 1s,
f(SCLK) = 100 kHz
CS = VDD,
Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000
5
nV–s
78
dB
NOTES: 10. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.
6
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