TLC5618 Datasheet, PDF (15/26 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
APPLICATION INFORMATION
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs, typical to within ± 0.5 LSB of final value.
external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
+ _{ǒ Ǔ ) ǒ Ǔ} + f(SCLK)max
1
tw _{CH min} tw _{CL min}
20 MHz
+ ǒ _{ǒ Ǔ} ) _{ǒ Ǔ}Ǔ ) _{ǒ Ǔ} ^{The digital update rate is limited by the chip-select period, which is:}
tp(CS) 16 tw _CH tw _CL
tsu _CS1
This equals an 810-ns or 1.23-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in, most
significant bit first. The falling edge of the SCLK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked
into the input register.
The 16 bits of data can be transferred with the sequence shown in Figure 19.
Program Bits
16 Bits
Data Bits
D15
D14
MSB (Input Word)
D13
D12
D11
12 Data Bits
D0
MSB (Data)
LSB (Data, Input Word)
Figure 19. Input Data Word Format
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