LMH6523 Datasheet, PDF (7/31 Pages) Texas Instruments – High Performance Quad DVGA

LMH6523
www.ti.com
Table 1. PIN FUNCTIONS (continued)
PIN NUMBER
SYMBOL
PIN CATEGORY
DESCRIPTION
32
ENBD
Digital Input
Channel D enable pin
Parallel Mode Digital Pins, MODE = Logic Low
49, 48, 47, 46, A0, A1, A2, A3, A4 Digital Input
45
Channel A attenuator control
54, 53, 52, 51, B0, B1, B2, B3, B4 Digital Input
50
Channel B attenuator control
19, 20, 21, 22, C0, C1, C2, C3, C4 Digital Input
23
Channel C attenuator control
24, 25, 26, 27, D0, D1, D2, D3, D4 Digital Input
28
Channel D attenuator control
Serial Mode Digital Pins, MODE = Logic High
SPI Compatible
45
SDO
Digital Output-
Open Collector
Serial Data Output (Requires external bias.)
46
SDI
Digital Input
Serial Data In
47
CSb
Digital Input
Chip Select
48
CLK
Digital Input
Clock
SNOSC88 – DECEMBER 2012
Table 2. PIN LIST
PIN
DESCRIPTION
1
GND
2
INA+
3
INA–
4
GND
5
MODE
6
GND
7
INB+
8
INB–
9
GND
10
GND
11
INC+
12
INC–
13
GND
14
GND
15
GND
16
IND+
17
IND–
18
GND
19
C0
20
C1
21
C2
22
C3
23
C4
24
D0
25
D1
26
D2
27
D3
PIN
DESCRIPTION
28
D4
29
OUTD–
30
OUTD+
31
+5VD
32
ENBD
33
+5VC
34
OUTC–
35
OUTC+
36
ENBC
37
ENBB
38
OUTB–
39
OUTB+
40
+5VB
41
ENBA
42
+5VA
43
OUTA–
44
OUTA+
45
A4 / SDO
46
A3 / SDI
47
A2 / CSb
48
A1 / CLK
49
A0
50
B4
51
B3
52
B2
53
B1
54
BO
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