LMH6523 Datasheet, PDF (22/31 Pages) Texas Instruments – High Performance Quad DVGA

LMH6523
SNOSC88 – DECEMBER 2012
Control Logic
LMH6523
Clock out
Chip Select out
Data Out
Data In
CLK
CSb
SDI
SDO
R
20
V+ (Logic High)
For SDO (MISO) pin only:
V_OH = V+,
V_OL = (V+) - {0.012 * (R+20) + Vcesat}
Vcesat ~= 0.2V
12mA
Max
Recommended:
R = 300 to 2000
V+ (Logic) = 2.5V to 5V
SVA-30206514
Figure 53. Internal Operation of the SDO pin
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R/Wb
Reserved
ADDR:
DATA
Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation.
Not used. Must be set to 0.
Address of register to be read or written.
In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In
a read operation this field is ignored.
SCLK
t_CSH
1^st clock
t_CSS
8^th clock
16^th clock
t_CSH
t_CSS
CSb
SDO
t_OZD
t_OD
D7 D1
t_ODZ
D0
Figure 54. Read Timing
SVA-30206511
PARAMETER
t_CSH
t_CSS
t_OZD
t_ODZ
t_OD
Table 4. Read Timing Data Output on SDO Pin
DESCRIPTION
Chip select hold time
Chip select setup time
Initial output data delay
High impedance delay
Output data delay
22
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