LMH6523 Datasheet, PDF (16/31 Pages) Texas Instruments – High Performance Quad DVGA

LMH6523
SNOSC88 – DECEMBER 2012
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BASIC CONNECTIONS
A voltage between 4.75 V and 5.25 V should be applied to the supply pin labeled +5V. Each supply pin should
be decoupled with a low inductance, surface-mount ceramic capacitor of 0.01µF as close to the device as
possible. Additional bypass capacitors of 0.1µF and 1nF are optional, but would provide bypassing over a wider
frequency range.
The outputs of the LMH6523 need to be biased to ground using inductors and output coupling capacitors of
0.01µF are recommended. The input pins are self biased to 2.5V and should be ac-coupled with 0.01µF
capacitors as well. The output bias inductors and ac-coupling capacitors are the main limitations for operating at
low frequencies. Larger values of inductance on the bias inductors and larger values of capacitance on the
coupling capacitors will give more low frequency range. Using bias inductors over 1 µH, however, may
compromise high frequency response due to unwanted parasitic loading on the amplifier output pins.
Each channel of the LMH6523 consists of a digital step attenuator followed by a low distortion 26 dB fixed gain
amplifier and a low impedance output stage. The attenuation is digitally controlled over a 31 dB range from 0dB
to 31dB. The LMH6523 has a 100Ω differential input impedance and a low, 20Ω, output impedance.
Each channel of the LMH6523 has an enable pin. Grounding the enable pin will put the channel in a power
saving shutdown mode. Additionally, there are two “on” states which gives the option of two power modes. High
Power Mode is selected by biasing the enable pins at 2.0 V or higher. The LMH6523 enable pins will self bias to
the Low Power State, alternatively supplying a voltage between 0.6V and 1.8V will place the channel in Low
Power Mode. If connected to a TRI-STATE buffer the LMH6523 enable pins will be in shutdown for a logic 0
output, in High Power Mode for a logic 1 state and they will self bias to Low Power Mode for the high impedance
state.
SOURCE
+5V
+
0.01 F
LOAD
50
0.01 F
IN+
OUT+
40.2
0.01 F
AC
¼
LMH6523
100
OUT-
50
0.01 F
IN -
40.2
0.01 F
5
1H
1H
A0 ± A4
Figure 44. LMH6523 Basic Connections Schematic
SVA-30206501
INPUT CHARACTERISTICS
The LMH6523 input impedance is set by internal resistors to a nominal 100Ω. Process variations will result in a
range of values. At higher frequencies parasitic reactances will start to impact the impedance. This characteristic
will also depend on board layout and should be verified on the customer’s system board.
At maximum gain the digital attenuator is set to 0 dB and the input signal will be much smaller than the output. At
minimum gain the output is 5 dB or more smaller than the input. In this configuration the input signal will begin to
clip against the ESD protection diodes before the output reaches maximum swing limits. The input signal cannot
swing more than 0.5V below the negative supply voltage (normally 0V) nor should it exceed the positive supply
voltage. The input signal will clip and cause severe distortion if it is too large. Because the input stage self biases
to approximately mid rail the supply voltage will impose the limit for input voltage swing.
At higher frequencies the LMH6523 input impedance is not purely resistive. In Figure 45 a circuit is shown that
matches the amplifier input impedance with a source that is 100Ω. This would be the case when connecting the
LMH6523 directly to a mixer. For an easy way to calculate the L and C circuit values there are several options for
online tools or down-loadable programs. The following tool might be helpful.
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