English
Language : 

CD74HC137_07 Datasheet, PDF (7/19 Pages) Texas Instruments – High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
◁
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
TEST
SYMBOL CONDITIONS VCC (V) MIN
25oC
TYP MAX
-40oC TO
85oC
-55oC TO 125oC
MIN MAX MIN MAX UNITS
HCT TYPES
Propagation Delay
An to any Y or Y
Address to Output
tPLH, tPHL CL = 50pF
tPLH, tPHL CL = 15pF
4.5
-
-
38
-
48
-
5
-
16
-
-
-
-
57
ns
-
ns
OE0 to any Y (HC137)
tPLH, tPHL CL = 50pF
4.5
-
-
35
-
44
-
53
ns
OE0 to any Y (HC237)
tPLH, tPHL CL = 50pF
4.5
-
-
33
-
41
-
60
ns
OE1 to any Y (HC137)
tTLH, tTHL CL = 50pF
4.5
-
-
37
-
46
-
56
ns
OE1 to any Y (HC237)
tTLH, tTHL CL = 50pF
4.5
-
-
35
-
44
-
53
ns
LE to any Y (HC137)
tTLH, tTHL CL = 50pF
4.5
-
-
44
-
55
-
66
ns
LE to any Y (HC237)
tTLH, tTHL CL = 50pF
4.5
-
-
42
-
53
-
63
ns
Power Dissipation
Capacitance, (Notes 3, 4)
CD74HC137
CPD CL = 15pF
5
-
19
-
-
-
-
-
pF
’HC237
CPD CL = 15pF
5
-
23
-
-
-
-
-
pF
Output Transition Time
tTLH, tTHL CL = 50pF
4.5
15
19
22
ns
Input Capacitance
CI
-
-
-
-
10
-
10
-
10
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuits and Waveforms
trCL
CLOCK
90%
10%
tfCL
50%
10%
tWL
tWL
+
tWH
=
I
fCL
50%
50%
tWH
VCC
GND
trCL = 6ns
CLOCK
2.7V
0.3V
tfCL = 6ns
tWL
+
tWH
=
I
fCL
3V
1.3V
0.3V
1.3V
1.3V
GND
tWL
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tr = 6ns
INPUT
90%
50%
10%
tf = 6ns
VCC
GND
tTHL
INVERTING
OUTPUT
tPHL
tTLH
90%
50%
10%
tPLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
tr = 6ns
INPUT
tTHL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
tPHL
tf = 6ns
3V
GND
tTLH
90%
1.3V
10%
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
 ▷