CD74HC137_07 Datasheet, PDF (2/19 Pages) Texas Instruments – High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
Pinout
CD54HC237 (CERDIP)
CD74HC137 (PDIP, TSSOP)
CD74HCT137 (PDIP, SOIC)
CD74HC237 (PDIP, SOIC, SOP, TSSOP)
CD74HCT237 (PDIP)
TOP VIEW
A₀ 1
A₁ 2
A₃ 3
LE 4
OE₁ 5
OE₀ 6
Y₇ 7
GND 8
16 V_CC
15 Y₀
14 Y₁
13 Y₂
12 Y₃
11 Y₄
10 Y₅
9 Y₆
Functional Diagram
1
A₀
A₁
2
3-BIT
LATCH
3
A₂
4
LE
5
OE₁
6
OE₀
HC/HCT HC/HCT
237 137
15
Y₀
Y₀
14
1 OF 8
Y₁
Y₁
DECODER ¹³
Y₂
Y₂
12
Y₃
Y₃
11
Y₄
Y₄
10
Y₅
Y₅
9
Y₆
Y₆
7
Y₇
Y₇
GND = 8
V_CC = 16
’HC137, ’HCT137 TRUTH TABLE
INPUTS
OUTPUTS
LE
OE₀
OE₁
A₂
A₁
A₀
Y₀
Y₁
Y₂
Y₃
Y₄
Y₅
Y₆
Y₇
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
L
X
X
X
X
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
L
L
H
L
H
H
L
H
H
H
H
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
H
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
X
X
X
Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
’HC237, ’HCT237 TRUTH TABLE
INPUTS
OUTPUTS
LE
OE₀
OE₁
A₂
A₁
A₀
Y₀
Y₁
Y₂
Y₃
Y₄
Y₅
Y₆
Y₇
X
X
H
X
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
L
X
X
X
Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2