CD74HC137_07 Datasheet, PDF (1/19 Pages) Texas Instruments – High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Data sheet acquired from Harris Semiconductor
SCHS146F
March 1998 - Revised October 2003
CD74HC137, CD74HCT137,
CD54HC237, CD74HC237,
CD74HCT237
High-Speed CMOS Logic, 3- to 8-Line
Decoder/Demultiplexer with Address Latches
[ /Title
(CD74
HC137
,
CD74
HCT13
7,
CD74
HC237
,
CD74
HCT23
7)
/Sub-
ject
(High
Speed
Features
• Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
•
Typical Propagation Delay of 13ns
15pF, T_A = 25^oC (CD74HC237)
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30%, of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Description
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE)
signal to isolate the outputs from select-input changes. A
“Low” LE makes the output transparent to the input and the
circuit functions as a one-of-eight decoder. Two Output
Enable inputs (OE₁ and OE₀) are provided to simplify
cascading and to facilitate demultiplexing. The
demultiplexing function is accomplished by using the A₀, A₁,
A₂ inputs to select the desired output and using one of the
other Output Enable inputs as the data input while holding
the other Output Enable input in its active state. In the
CD74HC137 and CD74HCT137 the selected output is a
“Low”; in the ’HC237 and CD74HCT237 the selected output is
a “High”.
Ordering Information
PART NUMBER
CD54HC237F3A
CD74HC137E
CD74HC137PW
CD74HC137PWR
CD74HC137PWT
CD74HC237E
CD74HC237M
CD74HC237MT
CD74HC237M96
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
The CD74HC137, CD74HCT137, ’HC237, and
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
CD74HC237NSR
CD74HC237PW
CD74HC237PWR
CD74HC237PWT
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
CD74HCT137E
-55 to 125
16 Ld PDIP
CD74HCT137MT
-55 to 125
16 Ld SOIC
CD74HCT137M96
-55 to 125
16 Ld SOIC
CD74HCT237E
-55 to 125
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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