CD74FCT653 Datasheet, PDF (7/9 Pages) Texas Instruments – FCT Interface Logic, Octal Bus Transceivers/ Registers, Open Drain (A Side), Three-State (B Side)

CD74FCT653, CD74FCT654
Switching t_r, t_f = 2.5ns, C_L = 50pF, R_L (Figures 3, 4)
25^oC
PARAMETER
Power Dissipation Capacitance
Min (Valley) V_OH (B Side) During Switching of Other
Outputs (Output Under Test Not Switching)
SYMBOL
C_PD
V_OHV
(Figure 1)
V_CC (V)
-
5
TYP
-
0.5
Max (Peak) V_OL During Switching of Other Outputs
V_OLP
5
1
(Output Under Test Not Switching)
(Figure 1)
Input Capacitance
C_I
-
-
Three-State Output Capacitance (B Side)
C_O
-
-
Off-State Output Capacitance (A Side)
C_O
-
-
NOTES:
8. 5V: minimum is at 4.75V for 0^oC to 70^oC, typical is at 5V.
9.
C_PD, measured
(per package) =
per flip-flop, is used
V_CC I_CC + Σ(V_CC2
to determine
f_I C_PD + V_O2
the dynamic
f_OC_L + V_CC
power consumption.
∆I_CC D) where:
PD
V_CC = supply voltage
∆I_CC = flow through current x unit load
C_L = output load capacitance
D = duty cycle of input high
f_O = output frequency
f_I = input frequency
0^oC TO 70^oC
MIN
MAX
-
-
-
-
-
-
-
10
-
15
-
15
UNITS
pF
V
V
pF
pF
pF
Test Circuits and Waveforms
t_r, t_f = 2.5ns
(NOTE 10) ^VI
3V
0
PULSE Z_O
GEN
R_T = Z_O
R_T
V_CC
V₀
DUT
C_L
50pF
7V
500Ω
R_L
500Ω
R_L
NOTE:
10. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z_OUT ≤ 50Ω;
t_f, t_r ≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
SWITCH POSITION
TEST
SWITCH
t_PLZ, t_PZL, Open Drain
Closed
t_PHZ, t_PZH, t_PLH, t_PHL
Open
DEFINITIONS:
C_L = Load capacitance, includes jig and probe
capacitance.
R_T = Termination resistance, should be equal to Z_OUT of
the Pulse Generator.
V_IN = 0V to 3V.
Input: t_r = t_f = 2.5ns (10% to 90%), unless otherwise specified
DATA
INPUT
t_SH
t_H
TIMING
INPUT
ASYNCHRONOUS CONTROL
t_REM
SYNCHRONOUS CONTROL
PRESET CLEAR
CLOCK ENABLE
ETC.
t_SH
t_H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
LOW-HIGH-LOW
PULSE
1.5V
t_W
HIGH-LOW-HIGH
PULSE
1.5V
FIGURE 3. PULSE WIDTH
8-7