CD74FCT653 Datasheet, PDF (1/9 Pages) Texas Instruments – FCT Interface Logic, Octal Bus Transceivers/ Registers, Open Drain (A Side), Three-State (B Side)

CD74FCT653,
Data sheet acquired from Harris Semiconductor
SCHS263
CD74FCT654
FCT Interface Logic, Octal Bus Transceivers/
January 1997
Registers, Open Drain (A Side), Three-State (B Side)
Features
• Buffered Inputs
• Typical Propagation Delay:
NOFOT_UsRRe ^E_CNCMEOOWS^MD_T^M_e^E_c^E_h^SN_n^I_o^GD_lo^NE_g^SD_y
6.8ns at V_CC = 5V, T_A = 25^oC, C_L = 50pF
• CD74FCT653
- Inverting
• CD74FCT654
- Non-Inverting
Description
The CD74FCT653 and CD74FCT654 octal bus transceiv-
ers/registers use a small geometry BiCMOS technology. The
output stage is a combination of bipolar and CMOS transistors
that limits the output HIGH level to two diode drops below V_CC.
This resultant lowering of output swing (0V to 3.7V) reduces
power bus ringing (a source of EMI) and minimizes V_CC
bounce and ground bounce and their effects during simulta-
neous output switching. The output configuration also
enhances switching speed and is capable of sinking 64mA.
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 64mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V_CC = 5V
• Controlled Output Edge Rates
• Input/Output Isolation to V_CC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
PART NUMBER
TEMP.
RANGE (^oC) PACKAGE
PKG.
NO.
The CD74FCT653 is an inverting type having open drains on
the A output and three state outputs on the B side. The
CD74FCT654 differs only in that it is a noninverting type. These
devices consist of bus transceiver circuits, D-Type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers.
Output Enables OEAB and OEBA are provided to control the
transceiver functions. SAB and SBA control pins are provided
to select whether real-time or stored data is transferred. The cir-
cuitry used for select control will eliminate the typical decoding
glitch that occurs in a multiplexer during the transition between
stored and real-time data. A LOW input level selects real-time
data and a HIGH selects stored data. The following examples
demonstrate the four fundamental bus management functions
that can be performed with the octal bus transceivers and regis-
ters.
CD74FCT653EN
0 to 70 24 Ld PDIP E24.3
CD74FCT654EN
0 to 70 24 Ld PDIP E24.3
CD74FCT653M
0 to 70 24 Ld SOIC M24.3
CD74FCT654M
0 to 70 24 Ld SOIC M24.3
NOTE: When ordering the suffix M packages, use the entire part
number. Add the suffix 96 to obtain the variant in the tape and reel.
Data on the A or B data bus, or both, can be stored in the inter-
nal D flip-flops by low to high transitions at the appropriate clock
pins (CAB or CBA) regardless of the select or enable control
pins. When SAB and SBA are in the real-time transfer mode, it
is also possible to store data without using the internal D-Type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.
Pinouts
CD74FCT653
(PDIP, SOIC)
TOP VIEW
CD74FCT654
(PDIP, SOIC)
TOP VIEW
CAB 1
SAB 2
OEAB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
CAB 1
SAB 2
OEAB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 VCC
23 CBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-1
File Number 2403.2