BQ29312A Datasheet, PDF (7/35 Pages) Texas Instruments – TWO-CELL, THREE-CELL, AND FOUR-CELL LITHIUM-ION OR LITHIUM-POLYMER BATTERY PROTECTION AFE

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BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
PW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
PIN ASSIGNMENTS
bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
RTH PACKAGE
(TOP VIEW)
OD
PMS
PACK
ZVCHG
VC2
CHG
VC3
SLEEP
VC4
REG
VC5
TOUT
SR1
XALERT
SR2
GND
SDATA
SCLK
ZVCHG
CHG
SLEEP
REG
TOUT
XALERT
TERMINAL
NAME
PIN NO.
RTH PW
BAT
22
1
DSG
23
2
VC1
24
3
VC2
1
4
VC3
2
5
VC4
3
6
VC5
4
7
SR1
5
8
SR2
6
9
WDI
7
10
CELL
8
11
GND
9
12
SCLK
10
13
SDATA 11
14
GND
12
15
XALERT 13
16
TOUT
14
17
REG
15
18
SLEEP
16
19
CHG
17
20
ZVCHG 18
21
PACK
19
22
PMS
20
23
OD
21
24
Terminal Functions
DESCRIPTION
Diode protected BAT+ terminal and primary power source.
Push-pull output discharge FET gate drive
Sense voltage input terminal for most-positive cell and balance current input for most-positive cell.
Sense voltage input terminal for second most-positive cell, balance current input for second most-positive cell
and return balance current for most-positive cell.
Sense voltage input terminal for third most-positive cell, balance current input for third most-positive cell and
return balance current for second most-positive cell.
Sense voltage input terminal for least-positive cell, balance current input for least-positive cell and return
balance current for third most-positive cell.
Sense voltage input terminal for most-negative cell, return balance current for least-positive cell.
Current sense positive terminal when charging relative to SR2
Current sense negative terminal when discharging relative to SR2 current sense terminal
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
Output of scaled value of the measured cell voltage.
Analog ground pin and negative pack terminal
Open-drain bidirectional serial interface clock with internal 10-kΩ pullup to V_(REG).
Open-drain bidirectional serial interface data with internal 10-kΩ pullup to V_(REG).
Connect to GND
Open-drain output used to indicate status register changes. With internal 100-kΩ pullup to V_(REG)
Provides thermistor bias current
Integrated 3.3-V regulator output
This pin is pulled up to V_(REG) internally, open or H level makes Sleep mode
Push-pull output charge FET gate drive
The ZVCHG FET drive is connected here
PACK positive terminal and alternative power source
0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.
NCH FET open-drain output
7