BQ29312A Datasheet, PDF (19/35 Pages) Texas Instruments – TWO-CELL, THREE-CELL, AND FOUR-CELL LITHIUM-ION OR LITHIUM-POLYMER BATTERY PROTECTION AFE

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bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
FUNCTION CTL: Function Control Register
FUNCTION CTL REGISTER (0x03)
7
6
5
4
3
2
0
0
TOUT
XSCD
SSCC
XOL
1
PACKOUT
0
VMEN
The FUNCTION CTL register enables and disables functions of the bq29312A.
FUNCTION CTL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring function.
0 = disable voltage monitoring (default). CELL output is pulled down to GND level.
1 = enable voltage monitoring.
FUNCTION CTL b1 (PACKOUT): This bit is used to translate the PACK input to the CELL pin when VMEN=1.
The pack voltage is divided by 25 and is presented on CELL regardless of the CELL_SEL register settings.
0 = disable PACK OUT (default).
1 = enable PACK OUT.
FUNCTION CTL b2 (XOL): This bit enables or disables the overcurrent sense function.
0 = enable overload sense (default).
1 = disable overload sense.
FUNCTION CTL b3 (XSCC): This bit enables or disables the short current sense function of charging.
0 = enable short-circuit current sense in charge direction (default).
1 = disable short-circuit current sense in charge direction.
FUNCTION CTL b4 (XSCD): This bit enables or disables the short current sense function of discharge.
0 = enable short-circuit current sense in discharge direction (default).
1 = disable short-circuit current sense in discharge direction.
FUNCTION CTL b5 (TOUT): This bit controls the power to the thermistor.
0 = thermistor power is off (default).
1 = thermistor power is on.
CELL SEL: Cell Select Register
7
6
5
CB3
CB2
CB1
CELL_SEL REGISTER (0x04)
4
3
CB0
CAL1
2
CAL0
1
CELL1
0
CELL0
This register determines cell selection for voltage measurement and translation, cell balancing, and the
operational mode of the cell voltage monitoring.
CELL_SEL b0–b1 (CELL0–CELL1): These two bits select the series cell for voltage measurement translation.
CELL1
0
0
1
1
CELL0
0
1
0
1
SELECTED CELL
VC4–VC5, Bottom series element (default)
VC4–VC3, Second lowest series element
VC3–VC2, Second highest series element
VC1–VC2, Top series element
CELL_SEL b2–b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block.
CAL1
0
0
1
1
CAL0
0
1
0
1
SELECTED MODE
Cell translation for selected cell (default)
Offset measurement for selected cell
Monitor the V_REF value for gain calibration
Monitor the V_REF directly value for gain calibration, bypassing the translation circuit
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