BQ29312A Datasheet, PDF (20/35 Pages) Texas Instruments – TWO-CELL, THREE-CELL, AND FOUR-CELL LITHIUM-ION OR LITHIUM-POLYMER BATTERY PROTECTION AFE

bq29312A
SLUS629A – JANUARY 2005 – REVISED AUGUST 2005
www.ti.com
CELL_SEL b4–b7 (CB0–CB3): These 4 bits select the series cell for cell balance bypass path.
CELL SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path.
0 = disable bottom series cell balance charge bypass path (default).
1 = enable bottom series cell balance charge bypass path.
CELL SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
CELL SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
CELL SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.
0 = disable series cell balance charge bypass path (default).
1 = enable series cell balance charge bypass path.
OLV: Overload Voltage Threshold Register
OLV REGISTER (0x05)
7
6
5
4
3
0
0
0
OLV4
OLV3
2
OLV2
1
OLV1
OLV (b4–b0): These five bits select the value of the overload threshold with a default of 00000.
OLV (b4–b0) configuration bits with corresponding voltage threshold
00000
00001
00010
00011
00100
00101
00110
00111
0.050 V
0.055 V
0.060 V
0.065 V
0.070 V
0.075 V
0.080 V
0.085 V
01000
01001
01010
01011
01100
01101
01110
01111
0.090 V
0.095 V
0.100 V
0.105 V
0.110 V
0.115 V
0.120 V
0.125 V
10000
10001
10010
10011
10100
10101
10110
10111
0.130 V
0.135 V
0.140 V
0.145 V
0.150 V
0.155 V
0.160 V
0.165 V
11000
11001
11010
11011
11100
11101
11110
11111
0
OLV0
0.170 V
0.175 V
0.180 V
0.185 V
0.190 V
0.195 V
0.200 V
0.205 V
OLT: Overload Blanking Delay Time Register
OLT REGISTER (0x06)
7
6
5
4
3
0
0
0
0
OLT3
2
OLT2
1
OLT1
OLT(b3–b0): These four bits select the value of the delay time for overload with a default of 0000.
OLT(b3–b0) configuration bits with corresponding delay time
0000
0001
0010
0011
1 ms
3 ms
5 ms
7 ms
0100
0101
0110
0111
9 ms
11 ms
13 ms
15 ms
1000
1001
1010
1011
17 ms
19 ms
21 ms
23 ms
1100
1101
1110
1111
0
OLT0
25 ms
27 ms
29 ms
31 ms
SCC: Short Circuit in Charge Configuration Register
7
SCCT3
6
SCCT2
5
SCCT1
SCC REGISTER (0x07)
4
3
SCCT0
SCCV3
2
SCCV2
1
SCCV1
0
SCCV0
20