ADS58C48 Datasheet, PDF (7/70 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

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ADS58C48
SLAS689 – MAY 2010
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 1.8 V, DRVDD = 1.8 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
DIGITAL INPUTS – RESET, SCLK, SDATA, SEN, SNRB_1, SNRB_2 and PDN
High-level input voltage
Low-level input voltage
RESET, SCLK, SDATA and SEN support
1.8 V and 3.3 V CMOS logic levels.
High-level input
current
SDATA, SCLK⁽¹⁾
SEN ⁽²⁾
V_HIGH = 1.8 V
V_HIGH = 1.8 V
Low-level input
current
SDATA, SCLK
SEN
V_LOW = 0 V
V_LOW = 0 V
DIGITAL OUTPUTS – CMOS INTERFACE (CHx_Dn, SDOUT)
1.3
V
0.4 V
10
µA
0
µA
0
µA
–10
µA
High-level output voltage
DRVDD – 0.1 DRVDD
V
Low-level output voltage
0 0.1 V
DIGITAL OUTPUTS – LVDS INTERFACE (CHx<>P/M, CLKOUTP/M)
V_ODH, High-level output voltage⁽³⁾
V_ODL, Low-level output voltage⁽³⁾
V_ODH, High-level output voltage⁽³⁾
V_ODL, Low-level output voltage⁽³⁾
Standard swing LVDS
Standard swing LVDS
Low swing LVDS⁽⁴⁾
Low swing LVDS⁽⁴⁾
V_OCM, Output common-mode voltage
275
–425
0.9
350 425 mV
–350 –275 mV
200
mV
–200
mV
1.05 1.25 V
(1) SDATA, SCLK have internal 170-kΩ pull-down resistor.
(2) SEN has internal 170-kΩ pull-up resistor to AVDD.
(3) With external 100-Ω termination.
(4) See the LVDS Output Data and Clock Buffers section in the Application Information.
DDnA_DPn/D+B1_PP
DDnA_MD/nD+B1M_M
V_OCM
Logic 0
V_ODL*
Logic 1
V_ODH*
V
GGNNDD
* With external 100-W termination
Figure 2. LVDS Output Voltage Levels
T0334-03
Copyright © 2010, Texas Instruments Incorporated
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