ADS58C48 Datasheet, PDF (41/70 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

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ADS58C48
SLAS689 – MAY 2010
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V_PP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,
DDR LVDS output interface, 32k point FFT (unless otherwise noted)
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
83
67.3
Fin = 20MHz
82.5
67.2
82
67.1
81.5
67
THD
81
66.9
80.5
66.8
80
SNR
66.7
79.5
66.6
79
66.5
25 30 35 40 45 50 55 60 65 70 75
Input Clock Duty Cycle (%)
Figure 40.
ANALOG POWER
vs
SAMPLING FREQUENCY
0.55
AVDD = 1.8V
0.5
Fin = 2.5MHz
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0
20 40 60 80 100 120 140 160 180 200
Sampling Frequency (MSPS)
Figure 41.
DIGITAL POWER
vs
SAMPLING FREQUENCY
1
Default after Reset
Digital Gain + Offset-Correction Enable
0.9
SNR Boost ON for 2ch’s (60MHz Filter)
SNR Boost ON for 4ch’s (60MHz Filter)
0.8
SNR Boost ON for 4ch’s + Digital Gain
+ Offset Correction
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20 40 60 80 100 120 140 160 180 200
Sampling Frequency (MSPS)
Figure 42.
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