ADS58C48 Datasheet, PDF (37/70 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

www.ti.com
ADS58C48
SLAS689 – MAY 2010
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V_PP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,
DDR LVDS output interface, 32k point FFT (unless otherwise noted)
PERFORMANCE ACROSS INPUT AMPLITUDE WITH SNRBoost ^3G DISABLED
100
68.4
Fin = 150MHz
90
68.1
SFDR dBFS
80
67.8
70
67.5
SNR dBFS
60
67.2
50
66.9
40
66.6
SFDR dBc
30
66.3
20
66
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10 −5 0
Input Amplitude (dBFS)
Figure 30.
PERFORMANCE ACROSS INPUT AMPLITUDE WITH SNRBoost ^3G ENABLED, 60-MHz BANDWIDTH
105
77.5
Fin = 150MHz
100
77
95
In−Band SFDR dBFS _76.5
90
76
85
75.5
80
In−Band SNR dBFS
75
75
74.5
70
74
65
73.5
60
73
55
In−Band SFDR dBc
72.5
50
72
45
71.5
40
71
−55 −50 −45 −40 −35 −30 −25 −20 −15 −10 −5 0
Input Amplitude (dBFS)
Figure 31.
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :ADS58C48
Submit Documentation Feedback
37