ADS58C48 Datasheet, PDF (39/70 Pages) Texas Instruments – Quad Channel IF Receiver with SNRBoost 3G

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ADS58C48
SLAS689 – MAY 2010
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 V_PP
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High Perf Mode disabled, 0 dB gain,
DDR LVDS output interface, 32k point FFT (unless otherwise noted)
SFDR ACROSS TEMPERATURE
vs
AVDD SUPPLY
SNR ACROSS TEMPERATURE
vs
AVDD SUPPLY
86
AVDD = 1.88V
85.5
67
Fin = 40MHz
85
AVDD = 1.92V
66.9
84.5
AVDD = 1.78V
AVDD = 1.82V
84
83.5
66.8
AVDD = 1.72V
83
AVDD = 1.68V
AVDD = 1.72V
AVDD = 1.78V
AVDD = 1.82V
AVDD = 1.88V
AVDD = 1.92V
Fin = 40MHz
82.5
66.7
82
AVDD = 1.68V
81.5
66.6
81
80.5
80
−40
−20
0
20
40
60
80
66.5
−40
−20
0
20
40
60
80
Temperature (°C)
Figure 34.
Temperature (°C)
Figure 35.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
85
66.8
Fin = 40MHz
84.8
66.79
84.6
66.78
84.4
SFDR
66.77
84.2
SNR
66.76
84
66.75
83.8
66.74
83.6
66.73
83.4
66.72
83.2
66.71
83
66.7
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
DRVDD SUPPLY (V)
Figure 36.
Copyright © 2010, Texas Instruments Incorporated
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