ADS5263_13 Datasheet, PDF (65/82 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC

www.ti.com
ADS5263
SLAS760C – MAY 2011 – REVISED JANUARY 2013
DIGITAL AVERAGING
The ADS5263 includes an averaging function where the ADC digital data from two (or four) channels can be
averaged. The averaged data is output on specific LVDS channels. Table 13 shows the combinations of the input
channels that can be averaged and the LVDS channels on which averaged data is available
Table 13. Using Channel Averaging
Averaged Channels
Channel 1, Channel 2
Channel 1, Channel 2
Channel 3, Channel 4
Channel 3, Channel 4
Channel 1, Channel 2, Channel 3, Channel 4
Channel 1, Channel 2, Channel 3, Channel 4
Output on Which Averaged Data Is
Available
OUT1A, OUT1B
OUT3A, OUT3B
OUT4A, OUT4B
OUT2A, OUT2B
OUT1A, OUT1B
OUT1A, OUT1B
Register Settings
Set <AVG OUT 1> = 10 and <EN AVG GLO> = 1
Set <AVG OUT 3> = 11 and <EN AVG GLO> = 1
Set <AVG OUT 4> = 10 and <EN AVG GLO> = 1
Set <AVG OUT 2> = 11 and <EN AVG GLO> = 1
Set <AVG OUT 1> = 11 and <EN AVG GLO> = 1
Set <AVG OUT 4> = 11 and <EN AVG GLO> = 1
PERFORMANCE WITH DIGITAL PROCESSING BLOCKS
The ADS5263 provides very high SNR along with high sampling rates. In applications where even higher SNR
performance is desired, digital processing blocks such as averaging and decimation filters can be used
advantageously to achieve this. Table 14 shows the improvement in SNR that can be achieved compared to the
default value, using these modes.
Table 14. SNR Improvement Using Digital Processing ⁽¹⁾
MODE
Default
With decimation-by-2 filter enabled
With decimation-by-4 filter enabled
With decimation-by-8 filter enabled
With two channels averaged and decimation-by-8 filter enabled
With four channels averaged
With four channels averaged and decimation-by-8 filter enabled
TYPICAL SNR, dBFS
84.5
86.7
87.7
88.6
91.3
89.6
93
TYPICAL IMPROVEMENT in SNR, dB
2.2
3.2
4.1
6.8
5.1
8.5
(1) Custom coefficients used for decimation-by-8 filter.
18-Bit Data Output With Digital Processing
As shown in Table 14, very high SNR can be achieved using the digital blocks. Now, the overall SNR is limited
by the quantization noise of the 16-bit output data. (16-bit quantization SNR = 6n + 1.76 = 16 × 6 + 1.76 = 97.76
dBFS.) To overcome this, the digital processing blocks (averaging and digital filters) automatically output 18-bit
data. With the two additional bits, the quantization SNR improves by 12 dB and no longer limits the maximum
SNR that can be achieved using the ADS5263. For example, with four channels averaged and the decimation-
by-8 filter, the typical SNR improves to about 94.5 dBFS using 18-bit data (an improvement of 1.5 dB over the
SNR with 16-bit data).
The 18-bit data can be output using the special 18× serialization mode (see Output LVDS Interface). Note that
the user can choose either the default 16× serialization (which takes the upper 16 bits of the 18-bit data) or the
18× serialization mode (that outputs all 18 bits).
FLEXIBLE MAPPING OF CHANNEL DATA TO LVDS OUTPUTS
ADS5263 has a mapping function by the use of which the digital data for any channel can be routed to any LVDS
output. So, as an example, in the 1-wire interface, the channel-1 ADC output can be output either on OUT1 pins
or on OUT2 or OUT3 or OUT4 pins.
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links :ADS5263
Submit Documentation Feedback
65