LM3S5791-IQC80-C5T Datasheet, PDF (633/1332 Pages) Texas Instruments – Stellaris LM3S5791 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5791 Microcontroller
Bit/Field
7:4
Name
EM1
Type
R/W
Reset
0x0
Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value
0x0
0x1
0x2
0x3
0x4
Event
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 1060).
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 1060).
Analog Comparator 2
This trigger is configured by the Analog Comparator Control
2 (ACCTL2) register (page 1060).
External (GPIO PB4)
This trigger is connected to the GPIO interrupt for PB4 (see
“ADC Trigger Source” on page 405).
Note:
PB4 can be used to trigger the ADC. However, the
PB4/AIN10 pin cannot be used as both a GPIO
and an analog input.
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 547).
0x6
PWM0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 1108).
0x7
PWM1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 1108).
0x8
PWM2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 1108).
0x9
PWM3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 1108).
0xA-0xE reserved
0xF
Always (continuously sample)
October 05, 2012
633
Texas Instruments-Production Data