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LM3S5791-IQC80-C5T Datasheet, PDF (293/1332 Pages) Texas Instruments – Stellaris LM3S5791 Microcontroller
NRND: Not recommended for new designs.
Stellaris® LM3S5791 Microcontroller
Bit/Field
8
7
6
5
4
3
2
1
0
Name
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
Description
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
October 05, 2012
293
Texas Instruments-Production Data