LM3S5791-IQC80-C5T Datasheet, PDF (456/1332 Pages) Texas Instruments – Stellaris LM3S5791 Microcontroller

NRND: Not recommended for new designs.
External Peripheral Interface (EPI)
Table 9-2. External Peripheral Interface Signals (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
EPI0S11
F10
PH5 (8)
I/O
TTL
EPI module 0 signal 11.
EPI0S12
K4
PF7 (8)
I/O
L9
PF4 (8)
TTL
EPI module 0 signal 12.
EPI0S13
K1
PG0 (8)
I/O
TTL
EPI module 0 signal 13.
EPI0S14
K2
PG1 (8)
I/O
TTL
EPI module 0 signal 14.
EPI0S15
K3
PG4 (8)
I/O
L8
PF5 (8)
TTL
EPI module 0 signal 15.
EPI0S16
F3
PJ0 (8)
I/O
TTL
EPI module 0 signal 16.
EPI0S17
B6
PJ1 (8)
I/O
TTL
EPI module 0 signal 17.
EPI0S18
K6
PJ2 (8)
I/O
TTL
EPI module 0 signal 18.
EPI0S19
M10
PJ3 (8)
I/O
B5
PD4 (10)
TTL
EPI module 0 signal 19.
EPI0S20
H2
PD2 (8)
I/O
TTL
EPI module 0 signal 20.
EPI0S21
H1
PD3 (8)
I/O
TTL
EPI module 0 signal 21.
EPI0S22
B7
PB5 (8)
I/O
TTL
EPI module 0 signal 22.
EPI0S23
A6
PB4 (8)
I/O
TTL
EPI module 0 signal 23.
EPI0S24
A4
PE2 (8)
I/O
TTL
EPI module 0 signal 24.
EPI0S25
B4
PE3 (8)
I/O
TTL
EPI module 0 signal 25.
EPI0S26
G3
PH6 (8)
I/O
TTL
EPI module 0 signal 26.
EPI0S27
H3
PH7 (8)
I/O
TTL
EPI module 0 signal 27.
EPI0S28
K11
PJ4 (8)
I/O
C6
PD5 (10)
TTL
EPI module 0 signal 28.
EPI0S29
K12
PJ5 (8)
I/O
A3
PD6 (10)
TTL
EPI module 0 signal 29.
EPI0S30
L10
PJ6 (8)
I/O
A2
PD7 (10)
TTL
EPI module 0 signal 30.
EPI0S31
C10
PG7 (9)
I/O
TTL
EPI module 0 signal 31.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
9.3 Functional Description
The EPI controller provides a glueless, programmable interface to a variety of common external
peripherals such as SDRAM x 16, Host Bus x8 and x16 devices, RAM, NOR Flash memory, CPLDs
and FPGAs. In addition, the EPI controller provides custom GPIO that can use a FIFO with speed
control by using either the internal write FIFO (WFIFO) or the non-blocking read FIFO (NBRFIFO).
The WFIFO can hold 4 words of data that are written to the external interface at the rate controlled
by the EPI Main Baud Rate (EPIBAUD) register. The NBRFIFO can hold 8 words of data and
samples at the rate controlled by the EPIBAUD register. The EPI controller provides predictable
operation and thus has an advantage over regular GPIO which has more variable timing due to
on-chip bus arbitration and delays across bus bridges. Blocking reads stall the CPU until the
transaction completes. Non-blocking reads are performed in the background and allow the processor
to continue operation. In addition, write data can also be stored in the WFIFO to allow multiple writes
with no stalls.
456
October 05, 2012
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