LM3S5791-IQC80-C5T Datasheet, PDF (458/1332 Pages) Texas Instruments – Stellaris LM3S5791 Microcontroller

NRND: Not recommended for new designs.
External Peripheral Interface (EPI)
9.3.2
9.4
// if here, then other one is active or interface no longer busy
cnt = (EPIRADDR0 – original_address) / EPIRSIZE0; // count of values read
cnt -= values_read_so_far;
// cnt is now number left in FIFO
while (cnt--)
value = EPIREADFIFO; // drain
The above algorithm can be optimized in code; however, the important point is to wait for the cancel
to complete because the external interface could have been in the process of reading a value when
the cancel came in, and it must be allowed to complete.
DMA Operation
The µDMA can be used to achieve maximum transfer rates on the EPI through the NBRFIFO and
the WFIFO. The µDMA has one channel for write and one for read. The write channel copies values
to the WFIFO when the WFIFO is at the level specified by the EPI FIFO Level Selects (EPIFIFOLVL)
register. The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is
at the level specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the
size per transaction, and the count of elements must be programmed in the µDMA. Note that both
non-blocking read register sets can be used, and they fill the NBRFIFO such that one runs to
completion, then the next one starts (they do not interleave). Using the NBRFIFO provides the best
possible transfer rate.
For blocking reads, the µDMA software channel (or another unused channel) is used for
memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). In
this situation, the µDMA stalls until the read is complete and is not able to service another channel
until the read is done. As a result, the arbitration size should normally be programmed to one access
at a time. The µDMA controller can also transfer from and to the NBRFIFO and the WFIFO using
the µDMA software channel in memory mode, however, the µDMA is stalled once the NBRFIFO is
empty or the WFIFO is full. Note that when the µDMA controller is stalled, the core continues
operation. See “Micro Direct Memory Access (μDMA)” on page 338 for more information on configuring
the µDMA.
The size of the FIFOs must be taken into consideration when configuring the µDMA to transfer data
to and from the EPI. The arbitration size should be 4 or less when writing to EPI address space and
8 or less when reading from EPI address space.
Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
1. Enable the EPI module using the RCGC1 register. See page 276.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register. See page 288. To
find out which GPIO port to enable, refer to “Signal Description” on page 454.
3. Set the GPIO AFSEL bits for the appropriate pins. See page 420. To determine which GPIOs to
configure, see Table 23-4 on page 1189.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See
page 422 and page 430.
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October 05, 2012
Texas Instruments-Production Data