TMS320DM6431 Datasheet, PDF (63/225 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6431
Digital Media Processor
SPRS342A – NOVEMBER 2006 – REVISED MARCH 2007
Table 3-3. DM6431 Default Module States (continued)
MODULE NAME
EMAC
McASP0
DDR2 Memory Contoller
EMIFA
McBSP0
I2C
UART0
HECC
PWM0
PWM1
PWM2
GPIO
TIMER0
TIMER1
C64x+ CPU
DEFAULT MODULE STATE
[PSC Register MDSTATn.STATE]
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable, if configuration pins AEM[2:0] = 000b
Enable, if configuration pins AEM[2:0] = Others [001b and 101b]
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
3.3.2 VPSS Clocks
The Video Processing SubSystem (VPSS) clocks are controlled via the VPSS_CLKCTL register. The
VPSS_CLKCTL register format is shown in Figure 3-2 and the bit field descriptions are given in Table 3-4.
31
16
RESERVED
R-0000 0000 0000 0000
15
RESERVED
5
4
3
2
1
0
RESERVED
PCLK
INV
RESERVED
R-0000 0000 000
LEGEND: R = Read; W = Write; -n = value after reset
R/W-00
R/W-0
R/W-00
Figure 3-2. VPSS_CLKCTL Register
Table 3-4. VPSS_CLKCTL Register Bit Description
BIT
NAME
DESCRIPTION
31:5
RESERVED
Reserved. Read-only, writes have no effect.
4:3
RESERVED
Reserved. For proper device operation, the user must only write "0" to these
bits.
PCLK polarity
2
PCLKINV
0 = VPSS receives normal PCLK [default].
1 = VPSS receives inverted PCLK.
1:0
RESERVED
Reserved. For proper device operation, the user must only write "0" to these
bits.
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Device Configurations
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