TMS320DM6431 Datasheet, PDF (169/225 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6431
Digital Media Processor
SPRS342A – NOVEMBER 2006 – REVISED MARCH 2007
6.10 Video Processing Sub-System (VPSS) Overview
The DM6431 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input
interface for external imaging peripherals (i.e., image sensors, video decoders, etc.).
The VPSS register memory mapping is shown in Table 6-28.
Table 6-28. VPSS Register Descriptions
HEX ADDRESS RANGE
REGISTER ACRONYM
0x01C7 3400
PID
0x01C7 3404
PCR
0x01C7 3408
-
0x01C7 3508
SDR_REG_EXP
0x01C7 350C -
-
0x01C7 3FFF
Description
Peripheral Revision and Class Information
VPSS Control Register
Reserved
SDRAM Non Real-Time Read Request Expand
Reserved
6.10.1 Video Processing Front-End (VPFE)
The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC). Together, these
modules provide DM6431 with a powerful and flexible front-end interface. This module is briefly described
below:
• The CCDC provides an interface to image sensors and digital video sources.
The VPFE register memory mapping is shown in Table 6-29.
Table 6-29. VPFE Register Address Range Descriptions
HEX ADDRESS RANGE
0x01C7 0400 – 0x01C7 07FF
0x01C7 3400 – 0x01C7 3FFF
ACRONYM
CCDC
VPSS
REGISTER NAME
VPFE – CCD Controller
VPSS Shared Buffer Logic Registers
6.10.1.1 CCD Controller (CCDC)
The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous
formats from video decoder devices. The following features are supported by the CCDC module.
• Conventional Bayer pattern format.
• Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to an
external timing generator.
• Interface to progressive and interlaced sensors.
• REC656/CCIR-656 standard (YCbCr 4:2:2 format, either 8- or 16-bit).
• YCbCr 4:2:2 format, either 8- or 16-bit with discrete H and VSYNC signals.
• Up to 16-bit input.
• Optical black clamping signal generation.
• Shutter signal control.
• Digital clamping and black level compensation.
• 10-bit to 8-bit A-law compression.
• Low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right
edges of each line are cropped from the output.
• Output range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area).
• Downsampling via programmable culling patterns.
• Control output to the DDR2 via an external write enable signal.
• Up to 16K pixels (image size) in both the horizontal and vertical direction.
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Peripheral Information and Electrical Specifications 169