TMS320DM6431 Datasheet, PDF (31/225 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6431
Digital Media Processor
SPRS342A – NOVEMBER 2006 – REVISED MARCH 2007
Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)
SIGNAL
NAME
ZWT
NO.
EM_A[3]/GP[11] B18
EM_A[2]/(CLE)/GP
[8]/
B16
(AEAW0/PLLMS0)
EM_A[1]/(ALE)/GP[
9]/
A16
(AEAW1/PLLMS1)
ZDU
NO.
D21
A20
B20
TYPE ⁽¹⁾
I/O/Z
I/O/Z
I/O/Z
OTHER ^{(2) (3)}
DESCRIPTION
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this pin is address bit 3 output EM_A[3].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this pin is address bit 2 output EM_A[2].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, this pin is address output EM_A[1].
This pin is multiplexed between EMIFA and GPIO.
EM_A[0]/
GP[7]/(AEM2)
EM_D0/GP[14]
EM_D1/GP[15]
EM_D2/GP[16]
EM_D3/GP[17]
EM_D4/GP[18]
EM_D5/GP[19]
EM_D6/GP[20]
EM_D7/GP[21]
EM_A[1]/(ALE)/GP[
9]/
(AEAW1/PLLMS1)
EM_A[2]/(CLE)/GP
[8]/
(AEAW0/PLLMS0)
EM_WAIT/
(RDY/BSY)
EM_OE
EM_WE
B17 C21
I/O/Z
IPD
DV_DD33
For EMIFA, this pin is Address output EM_A[0], which is the least
significant bit on a 32-bit word address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the
address.
D16 E21
I/O/Z
IPD
DV_DD33
D18 G20
I/O/Z
IPD
DV_DD33
D17 E22
I/O/Z
IPD
DV_DD33
E16 F20
E18 G21
I/O/Z
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
These pins are multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 001), these pins are the 8-bit bi-directional
data bus (EM_D[7:0]).
E17 F22
I/O/Z
IPD
DV_DD33
F16 F21
I/O/Z
IPD
DV_DD33
F17 H20
I/O/Z
IPD
DV_DD33
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 1, AEM[2:0] = 001)
A16 B20
I/O/Z
IPD
DV_DD33
This pin is multiplexed between EMIFA (NAND) and GPIO.
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
B16 A20
I/O/Z
IPD
DV_DD33
This pin is multiplexed between EMIFA (NAND) and GPIO.
When used for EMIFA (NAND), this pin is the Command Latch Enable
output (CLE).
E15 D20
D15 D19
E14 C19
I/O/Z
I/O/Z
I/O/Z
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
When used for EMIFA (NAND), this pin is read enable output (RE).
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_CS2/GP[12] C19 C22
I/O/Z
IPD
DV_DD33
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
This is the chip select for the default boot and ROM boot modes.
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
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