TMS320C6742_15 Datasheet, PDF (63/187 Pages) Texas Instruments – TMS320C6742™ Fixed- and Floating-Point DSP

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TMS320C6742
SPRS587E – JUNE 2009 – REVISED MARCH 2014
6.4.3 Reset Electrical Data Timings
Table 6-1 assumes testing over the recommended operating conditions.
Table 6-1. Reset Timing Requirements (⁽¹⁾, ⁽²⁾)
1.2V
1.1V
1.0V
NO.
UNIT
MIN MAX MIN MAX MIN MAX
1 t_w(RSTL)
2 t_su(BPV-RSTH)
3 t_h(RSTH-BPV)
4 ^td(RSTH-
RESETOUTH)
Pulse width, RESET/TRST low
Setup time, boot pins valid before RESET/TRST high
Hold time, boot pins valid after RESET/TRST high
RESET high to RESETOUT high; Warm reset
RESET high to RESETOUT high; Power-on Reset
100
20
20
4096
6169
100
20
20
4096
6169
100
20
20
4096
6169
ns
ns
ns
cycles ⁽³⁾
5 t_{d(RSTL-RESETOUTL)} Delay time, RESET/TRST low to RESETOUT low
14
16
20
ns
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-5 for details.
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
Power
Supplies
Ramping
OSCIN
Clock Source Stable
Power Supplies Stable
1
RESET
TRST
RESETOUT
Boot Pins
4
2
3
Config
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
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Peripheral Information and Electrical Specifications
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