TMS320C6742_15 Datasheet, PDF (132/187 Pages) Texas Instruments – TMS320C6742™ Fixed- and Floating-Point DSP

TMS320C6742
SPRS587E – JUNE 2009 – REVISED MARCH 2014
www.ti.com
6.15.2 SPI Electrical Data/Timing
6.15.2.1 Serial Peripheral Interface (SPI) Timing
The following tables and timing diagrams assume testing over recommended operating conditions.
Table 6-53. General Timing Requirements for SPI1 Master Modes⁽¹⁾
NO.
1 t_c(SPC)M
2 t_w(SPCH)M
3 t_w(SPCL)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
Polarity = 0, Phase = 0,
to SPI1_CLK rising
4 t_{d(SIMO_SPC)M}
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK ⁽³⁾
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5 t_{d(SPC_SIMO)M}
Delay, subsequent bits valid on
SPI1_SIMO after transmit edge
of SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Output hold time, SPI1_SIMO _{from SPI1_CLK rising}
6 t_{oh(SPC_SIMO)M} valid after receive edge of
SPI1_CLK
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Polarity = 0, Phase = 1,
Input Setup Time, SPI1_SOMI _{to SPI1_CLK rising}
7 t_{su(SOMI_SPC)M} valid before receive edge of
SPI1_CLK
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
8 t_{ih(SPC_SOMI)M}
Input Hold Time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
1.2V
MIN
MAX
20 ⁽²⁾
256P
0.5M-1
0.5M-1
5
-0.5M+5
5
-0.5M+5
5
5
5
5
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.5
1.5
1.5
1.5
4
4
4
4
1.1V
MIN
MAX
30 ⁽²⁾
256P
0.5M-1
0.5M-1
5
-0.5M+5
5
-0.5M+5
5
5
5
5
0.5M-3
0.5M-3
0.5M-3
0.5M-3
1.5
1.5
1.5
1.5
5
5
5
5
1.0V
MIN
MAX
40 ⁽²⁾
256P
0.5M-1
0.5M-1
6
UNIT
ns
ns
ns
-0.5M+6
ns
6
-0.5M+6
6
6
ns
6
6
0.5M-3
0.5M-3
ns
0.5M-3
0.5M-3
1.5
1.5
ns
1.5
1.5
6
6
ns
6
6
(1) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
132 Peripheral Information and Electrical Specifications
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