TMS320C6742_15 Datasheet, PDF (165/187 Pages) Texas Instruments – TMS320C6742™ Fixed- and Floating-Point DSP

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TMS320C6742
SPRS587E – JUNE 2009 – REVISED MARCH 2014
6.21 Timers
The timers support the following features:
• Configurable as single 64-bit timer or two 32-bit timers
• Period timeouts generate interrupts, DMA events or external pin events
• 8 32-bit compare registers
• Compare matches generate interrupt events
• Capture capability
• 64-bit Watchdog capability (Timer64P1 only)
Table 6-78 lists the timer registers.
TIMER64P 0 BYTE
ADDRESS
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
TIMER64P 1 BYTE
ADDRESS
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
Table 6-78. Timer Registers
ACRONYM
REGISTER DESCRIPTION
REV
EMUMGT
GPINTGPEN
GPDATGPDIR
TIM12
TIM34
PRD12
PRD34
TCR
TGCR
WDTCR
REL12
REL34
CAP12
CAP34
INTCTLSTAT
CMP0
CMP1
CMP2
CMP3
CMP4
CMP5
CMP6
CMP7
Revision Register
Emulation Management Register
GPIO Interrupt and GPIO Enable Register
GPIO Data and GPIO Direction Register
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
Timer Interrupt Control and Status Register
Compare Register 0
Compare Register 1
Compare Register 2
Compare Register 3
Compare Register 4
Compare Register 5
Compare Register 6
Compare Register 7
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Peripheral Information and Electrical Specifications 165
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