ADS62P49 Datasheet, PDF (63/76 Pages) Texas Instruments – Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009
CLKOUTM
CLKOUTP
DA0, DB0 D0
D1
D0
D1
DA2, DB2 D2
D3
D2
D3
DA4, DB4 D4
D5
D4
D5
DA6, DB6 D6
D7
D6
D7
DA8, DB8 D8
D9
D8
D9
DA10, DB10 D10 D11 D10 D11
DA12, DB12 D12 D13 D12 D13
Sample N
Sample N + 1
T0110-05
Figure 106. DDR LVDS Interface
LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 107. The buffer is designed to present an
output impedance of 100 Ω (Rout). The differential outputs can be terminated at the receive end by a 100-Ω
termination.
The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the
receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its
value cannot be changed.
Copyright © 2009, Texas Instruments Incorporated
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