ADS62P49 Datasheet, PDF (29/76 Pages) Texas Instruments – Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009
A7–A0 IN HEX
76
D7
D6
D5
D4
D3
D2
D1
D0
0
0
<OFFSET PEDESTAL – Common/CH B>
D5-D0
<OFFSET PEDESTAL – Common/CH B>
When the offset correction is enabled, the final converged value (after the offset is corrected) will
be the ideal ADC mid-code value (=8192 for P49/48, = 2048 for P29/28). A pedestal can be
added to the final converged value by programming these bits. So, the final converged value will
be = ideal mid-code + PEDESTAL. See "Offset Correction" in application section.
Applies to channel B (only with independent control).
011111 PEDESTAL = 31 LSB
011110 PEDESTAL = 30 LSB
011101 PEDESTAL = 29 LSB
….
000000 PEDESTAL = 0
….
111111 PEDESTAL = –1 LSB
111110 PEDESTAL = –2 LSB
….
100000 PEDESTAL = –32 LSB
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28