PCI2060 Datasheet, PDF (62/76 Pages) Texas Instruments – Asynchronous PCI-to-PCI Bridge

Extension Registers
5.9 P_SERR Status Register (6Ah)
The P_SERR status register indicates the cause of P_SERR assertion. See Table 5−9 for a complete
description of the register contents.
Bit Number
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
0
Table 5−9. P_SERR Status Register
BIT
FIELD NAME
DESCRIPTION
7 RSVD
Reserved. Returns 0b when read.
6 DELAYED_READ_TO
Master delayed read time-out. P_SERR is asserted since the PCI2060 bridge was unable to read data
from the target after 224 attempts.
5 DELAYED_WRITE_TO Master delayed write time-out. P_SERR is asserted since the PCI2060 bridge was unable to deliver
delayed write data after 224 attempts.
4 MASTER_ABORT_PW Master abort on posted write transactions. P_SERR is asserted since the PCI2060 bridge received a
master abort when attempting to deliver posted write data.
3 TARGET_ABORT_PW Target abort on posted writes. P_SERR is asserted since the PCI2060 bridge received a target abort
when delivering posted write data.
2 POSTED_WRITE_TO
Master posted write time-out. P_SERR is asserted since the PCI2060 bridge was unable to deliver
posted write data to the target after 224 attempts.
1 POSTED_WRITE_PERR Posted write parity error. P_SERR is asserted since a posted write data parity error was detected on
the target bus.
0 RSVD
Reserved. Returns 0b when read.
5.10 Capability ID Register (DCh)
The capability ID register identifies the linked list item as the register for PCI power management. The
capability ID register is read-only and returns 01h when read, which is the unique ID assigned by the PCI SIG
for the PCI location of the capabilities pointer and the value.
Bit Number
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
1
5.11 Next Item Pointer Register (DDh)
The next item pointer register indicates the next item in the linked list of PCI power-management capabilities.
The next-item pointer returns E4h in CompactPCI mode, indicating that the PCI206 bridge supports more than
one extended capability, but in all other modes returns 00h, indicating that only one extended capability is
provided.
Bit Number
7
6
5
4
3
2
1
0
Reset State
1
1
1
0
0
1
0
0
54 SCPS096A
April 2005