PCI2060 Datasheet, PDF (55/76 Pages) Texas Instruments – Asynchronous PCI-to-PCI Bridge

Configuration Header Space
4.31 Bridge Control Register (3Eh)
The bridge control register provides extensions to the command register that are specific to a bridge. The
bridge control register provides many of the same controls for the secondary interface that are provided by
the command register for the primary interface. See Table 4−15 for a complete description of the register
contents.
Bit Number 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset State 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−15. Bridge Control Register
BIT FIELD NAME
DESCRIPTION
15:12 RSVD
Reserved. Returns 0h when read.
11 DTSERR
Discard timer SERR enable. This bit controls the assertion of P_SERR on the primary interface when either the
primary discard timer or the secondary discard timer expires and a delayed transaction is discarded from a queue
in the bridge.
0 = Do not assert P_SERR on the primary bus as a result of expiration of either the primary discard timer or
the secondary discard timer
1 = Assert P_SERR on the primary bus if either the primary discard timer or the secondary discard timer
expires and a delayed transaction is discarded
10 DTSTATUS
Discard timer status. This bit is set to a 1b when either the primary discard timer or the secondary discard timer
expires and a delayed completion is discarded from a queue in the bridge.
0 = No discard timer error
1 = Discard timer error
9 SEC_DT
Secondary discard timer. Selects the number of PCI clocks that the PCI2060 bridge will wait for a master on the
secondary bus to repeat a delayed transaction request. The counter starts once the delayed completion (the
completion of the delayed transaction on the primary bus) has reached the head of the downstream queue of the
bridge (that is, all ordering requirements have been satisfied and the bridge is ready to complete the delayed
transaction with the initiating master on the secondary bus). If the master does not repeat the transaction before
the counter expires, then the bridge deletes the delayed transaction from its queue and sets the discard timer
status bit.
0 = The secondary discard timer counts 215 PCI clock cycles
1 = The secondary discard timer counts 210 PCI clock cycles
8 PRI_DIS
Primary discard timer. Selects the number of PCI clocks that the bridge will wait for a master on the primary bus to
repeat a delayed transaction request. The counter starts once the delayed completion (the completion of the
delayed transaction on the secondary interface) has reached the head of the upstream queue of the bridge (that is,
all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the
initiating master on the primary bus). If the master does not repeat the transaction before the counter expires,
then the bridge deletes the delayed transaction from its queue and sets the discard timer status bit.
0 = The primary discard timer counts 215 PCI clock cycles
1 = The primary discard timer counts 210 PCI clock cycles
7 FBB_EN
Fast back-to-back enable. This bit controls the ability of the PCI2060 bridge to generate fast back-to-back
transactions to different devices on the secondary interface.
0 = The PCI2060 bridge is disabled to generate fast back-to-back transactions on the secondary PCI bus
1 = The PCI2060 bridge is enabled to generate fast back-to-back transactions on the secondary PCI bus
6 SRST
Secondary bus reset. Setting this bit to 1b forces the assertion of S_RST on the secondary interface. The S_RST
is asserted by the bridge whenever this bit is set or the P_RST terminal on the primary bus is asserted. When this
bit is cleared, S_RST on the secondary bus is asserted whenever the primary interface RST is asserted.
0 = Do not force the assertion of the S_RST
1 = Force the assertion of the S_RST
April 2005
SCPS096A
47