PCI2060 Datasheet, PDF (46/76 Pages) Texas Instruments – Asynchronous PCI-to-PCI Bridge

Configuration Header Space
4.2 Device ID Register (02h)
The value in this 16-bit read-only register is assigned by the device manufacturer and identifies the type of
device. The device ID for the PCI2060 asynchronous bridge is AC2Ch.
Bit Number 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset State 1
0
1
0
1
1
0
0
0
0
1
0
1
1
0
0
4.3 Primary Command Register (04h)
The primary command register provides basic control over the PCI2060’s ability to respond to and/or perform
PCI accesses. Bits [15:11] are reserved for future use and must return 00000b. See Table 4−2 for a complete
description of the register contents.
Bit Number 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reset State 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4−2. Primary Command Register
BIT FIELD NAME
DESCRIPTION
15:11 RSVD
Reserved. Returns 00000b when read.
10 INT_DISABLE INTx disable. This bit enables or disables device-specific interrupts. The PCI2060 bridge does not generate any
interrupts internally. This bit is read-only and returns 0b when it is read.
9 FBB_ENB
Fast back-to-back enable
0 = The PCI2060 bridge does not generate back-to-back transactions on the primary bus.
1 = The PCI2060 bridge generates back-to-back transactions on the primary bus.
8 SERR_ENB
P_SERR enable
0 = Disables the signaling of P_SERR by PCI2060 bridge
1 = Enables the signaling of P_SERR by PCI2060 bridge
7 STEP_ENB
Address/data stepping control. The PCI2060 bridge does not support address/data stepping. This bit is read-only
and returns 0b when it is read.
6 PERR_ENB
Parity error response enable
0 = The PCI2060 bridge must ignore any address or data parity errors that it detects on the primary bus and
continue normal operation.
1 = The PCI2060 bridge must take the appropriate action when any address or data parity errors are detected
on the primary bus.
5 VGA_ENB
VGA palette snoop enable. When set, the PCI2060 bridge passes I/O writes on the primary PCI bus with
addresses 3C6h, 3C8h, and 3C9h inclusive of ISA aliases (that is, only P_AD[9:0] are included in the decode).
4 MWI_ENB
Memory write-and-invalidate enable. The PCI2060 bridge generates memory write-and-invalidate transactions
only when operating on behalf of another master whose memory write-and-invalidate transaction is crossing the
PCI2060 bridge. This bit is read-only and returns 0b when it is read.
3 SPECIAL
Special cycle enable. The PCI2060 bridge does not respond to special cycle transactions. This bit is read-only
and returns 0b when it is read.
2 MASTER_ENB Bus master enable
0 = The PCI2060 bridge does not initiate I/O or memory transactions on the primary bus and does not
respond to I/O or memory transactions on the secondary bus.
1 = The PCI2060 bridge is enabled to be an initiator on the primary bus and responds to I/O or memory
transactions on the secondary bus.
1 MEMORY_ENB Memory space enable
0 = The PCI2060 bridge does not respond to the memory transactions on the primary bus.
1 = The PCI2060 bridge responds to the memory transactions on the primary bus.
0 IO_ENB
I/O space enable
0 = The PCI2060 bridge does not respond to the I/O transactions on the primary bus.
1 = The PCI2060 bridge responds to the I/O transactions on the primary bus.
38 SCPS096A
April 2005