PCI2060 Datasheet, PDF (27/76 Pages) Texas Instruments – Asynchronous PCI-to-PCI Bridge

Principles of Operation
Table 3−5. Write Transaction Forwarding
TYPE OF TRANSACTION
Memory write
Memory write-and-invalidate
I/O write
Type 1 configuration write
TYPE OF FORWARDING
Posted
Posted
Delayed
Delayed
3.4.1 Posted Write Transaction
All memory write and memory write-and-invalidate transactions are handled as posted write transactions and
must be completed on the destination bus. The PCI2060 bridge has two 64-doubleword posted write FIFOs;
one for upstream transaction and the other for downstream transactions (these FIFOs are shared with delayed
request transactions).
When a posted write transaction is to be forwarded across the bridge, the PCI2060 bridge asserts the DEVSEL
with medium timing and the TRDY in the same cycle. Due to the asynchronous clock implementation, the
PCI2060 bridge requires eight doublewords of free space in the FIFO before it accepts any posted write
transactions.
The PCI2060 bridge continues to accept write data until one of the following events occurs:
• The initiator terminates the transaction by deasserting FRAME and IRDY.
• An internal write address boundary is reached, such as a cache line boundary or an aligned 4-KB
boundary, depending on the transaction type.
• The posted write data buffer fills up.
When one of the last two events occurs, the PCI2060 bridge returns a target disconnect to the requesting
initiator to terminate the transaction.
Once the PCI2060 bridge makes a request for the target bus and receives the grant for the target bus, the
PCI2060 bridge asserts FRAME and drives the stored write address out on the target bus when the target bus
is idle. On the next cycle, the PCI2060 bridge drives the first doubleword of the write data and continues to
transfer write data until all write data corresponding to that transaction is delivered.
The PCI2060 bridge ends the transaction on the target bus when one of the following conditions is met:
• All posted write data has been delivered to the target.
• The target returns a target disconnect or a target retry (the PCI2060 bridge then starts another transaction
to deliver the rest of the write data).
• The target returns a target abort (the PCI2060 bridge discards remaining write data).
• The master latency timer expires and the PCI2060 bridge no longer has the target bus grant (the PCI2060
then starts another transaction to deliver remaining write data).
The PCI2060 bridge handles memory write-and-invalidate transactions in two different ways:
• If bit 1 (MWI_MW_CONVERSION) in the TI diagnostic register (offset F0h) is cleared to 0b, and the
PCI2060 bridge has FIFO space for a full cache line, then the PCI2060 bridge accepts the memory
write-and-invalidate transaction. If the PCI2060 bridge does not have enough FIFO space for a full cache
line, then the bridge converts the memory write-and-invalidate transaction to the memory transaction. The
PCI2060 bridge waits until a full cache line of data is in the FIFO before initiating a memory
write-and-invalidate transaction on the destination bus.
• If the MWI_MW_CONVERSION bit is set to 1b, then the bridge converts all memory write-and-invalidate
transactions to memory write transactions before putting them in the FIFO.
April 2005
SCPS096A
19