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MSP430F23X Datasheet, PDF (62/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547F – JUNE 2007 – REVISED APRIL 2011
www.ti.com
12-bit ADC, Power Supply and Input Range Conditions(1)
over recommended operating free-air temperature range (unless otherwise noted)
AVCC
V(P6.x/Ax)
IADC12
PARAMETER
Analog supply voltage
Analog input voltage
range (2)
Operating supply current
into AVCC terminal(3)
TEST CONDITIONS
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
All P6.0/A0 to P6.7/A7 terminals, Analog inputs
selected in ADC12MCTLx register,
P6Sel.x = 1, 0 ≤ × ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
fADC12CLK = 5 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
VCC
2.2 V
3V
IREF+
Operating supply current
into AVCC terminal(4)
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 1
fADC12CLK = 5 MHz,
ADC12ON = 0, REFON = 1, REF2_5V = 0
3V
2.2 V
3V
CI
Input capacitance(5)
Only one terminal can be selected at one time,
P6.x/Ax
2.2 V
RI
Input MUX ON
resistance (5)
0 V ≤ VAx ≤ VAVCC
3V
MIN TYP
2.2
MAX UNIT
3.6 V
0
0.65
0.8
0.5
0.5
0.5
VAVCC V
0.8
mA
1
0.7 mA
0.7
mA
0.7
40 pF
2000 Ω
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC12.
(4) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables settling of the built-in reference before starting an A/D conversion.
(5) Not production tested, limits verified by design.
12-Bit ADC, External Reference(1)
over recommended operating free-air temperature range (unless otherwise noted)
VeREF+
VREF–/VeREF–
(VeREF+ –
VREF–/VeREF–)
IVeREF+
IVREF–/VeREF–
PARAMETER
Positive external reference voltage input
Negative external reference voltage input
Differential external reference voltage input
Static leakage current
Static leakage current
TEST CONDITIONS
VeREF+ > VREF–/VeREF– (2)
VeREF+ > VREF–/VeREF– (3)
VeREF+ > VREF–/VeREF– (4)
0 V ≤ VeREF+ ≤ VAVCC
0 V ≤ VeREF– ≤ VAVCC
VCC
2.2 V/3 V
2.2 V/3 V
MIN MAX UNIT
1.4 VAVCC V
0 1.2 V
1.4 VAVCC V
±1 µA
±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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