MSP430F23X Datasheet, PDF(17/93 Page) Texas Instruments

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MSP430F23X Datasheet, PDF (17/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547F â JUNE 2007 â REVISED APRIL 2011

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset

vector (0xFFFE) contains 0xFFFF (for example, if flash is not programmed) the CPU enters LPM4 after

power-up.

Table 7. Interrupt Vector Addresses

INTERRUPT SOURCE

Power-up

External reset

Watchdog

Flash key violation

PC out of range(1)

NMI

Oscillator fault

Flash memory access violation

Timer_B7 (4)

Comparator_A+

Watchdog timer+

Timer_A3

USCI_A0/USCI_B0 receive

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit

USCI_B0 I2C receive / transmit

ADC12 (8)

INTERRUPT FLAG

PORIFG

WDTIFG

RSTIFG

KEYV

(see (2))

NMIIFG

OFIFG

ACCVIFG (2) (3)

TBCCR0 CCIFG(5)

TBCCR1 to TBCCR6 CCIFGs,

TBIFG(2) (5)

CAIFG

WDTIFG

TACCR0 CCIFG(5)

TACCR1 CCIFG

TACCR2 CCIFG TAIFG(2)(5)

UCA0RXIFG, UCB0RXIFG(2)(6)

UCA0TXIFG, UCB0TXIFG(2)(7)

ADC12IFG (2) (5)

I/O port P2 (eight flags)

I/O port P1 (eight flags)

USCI_A1/USCI_B1 receive

USCI_B1 I2C status

USCI_A1/USCI_B1 transmit

USCI_B1 I2C receive / transmit

Reserved (9) (10)

P2IFG.0 to P2IFG.7(2)(5)

P1IFG.0 to P1IFG.7(2)(5)

UCA1RXIFG, UCB1RXIFG(2)(6)

UCA1TXIFG, UCB1TXIFG(2)(7)

Reserved

SYSTEM INTERRUPT WORD ADDRESS

PRIORITY

Reset

0xFFFE

31, highest

(Non)maskable

Maskable

0xFFFC

0xFFFA

0xFFF8

0xFFF6

0xFFF4

0xFFF2

0xFFF0

0xFFEE

0xFFEC

0xFFEA

0xFFE8

0xFFE6

0xFFE4

0xFFE2

0xFFE0

0xFFDE to 0xFFC0

15 to 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF) or

from within unused address range.

(2) Multiple source flags

(3) (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.

(4) Timer_B7 in MSP430F24x(1)/MSP430F2410 family has seven CCRs, Timer_B3 in MSP430F23x family has three CCRs. In Timer_B3,

there are only interrupt flags TBCCR0 CCIFG, TBCCR1 CCIFG, and TBCCR2 CCIFG, and the interrupt enable bits TBCCTL0 CCIE,

TBCCTL1 CCIE, and TBCCTL2 CCIE.

(5) Interrupt flags are located in the module.

(6) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(7) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

(8) ADC12 is not implemented in the MSP430F24x1 family.

(9) The address 0xFFDE is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A

zero disables the erasure of the flash if an invalid password is supplied.

(10) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if

necessary.

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