MSP430F23X Datasheet, PDF (24/93 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F23x
MSP430F24x(1)
MSP430F2410
SLAS547F – JUNE 2007 – REVISED APRIL 2011
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Timer_B3 (MSP430F23x Devices)
Timer_B3 is a 16-bit timer/counter with seven capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
INPUT PIN NUMBER
43 - P4.7
43 - P4.7
36 - P4.0
36 - P4.0
37 - P4.1
37 - P4.1
38 - P4.2
38 - P4.2
Table 18. Timer_B3 Signal Connections
DEVICE INPUT
SIGNAL
TBCLK
ACLK
SMCLK
TBCLK
TB0
TB0
DV_SS
DV_CC
TB1
TB1
DV_SS
DV_CC
TB2
TB2
DV_SS
DV_CC
MODULE INPUT
NAME
TBCLK
ACLK
SMCLK
INCLK
CCI0A
CCI0B
GND
V_CC
CCI1A
CCI1B
GND
V_CC
CCI2A
CCI2B
GND
V_CC
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
NA
CCR0
TB0
CCR1
TB1
CCR2
TB2
OUTPUT PIN
NUMBER
36 - P4.0
ADC12 (internal)
37 - P4.1
ADC12 (internal)
38 - P4.2
Universal Serial Communications Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols, such as SPI (3 or 4 pin) or I²C, and asynchronous combination protocols, such as
UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
The USCI A module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
The USCI B module provides support for SPI (3 or 4 pin) and I²C.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12 (MSP430F23x, MSP430F24x, and MSP430F2410 Devices)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any
CPU intervention.
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