TLC8188 Datasheet, PDF (6/12 Pages) Texas Instruments – 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR

TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
timing requirements
PARAMETER
Serial Interface
tw(SCKH)
SCK high pulse duration
tw(SCKL)
SCK low pulse duration
tsu(SSU)
Data (SDI) to SCK setup time
th(SH)
SDI to SCK hold time
tsu(SCE)
SCK to SEN setup time
tw(SEN)
SEN pulse duration
tsu(SEC)
SEN to SCK setup time
Parallel Interface
tw(STB)
tsu(D)
th(DH)
tsu(ADS)
th(ADH)
td(OPZI)
td(OPZE)
td(OPDV)
Output
Strobe pulse duration
Data to strobe setup time
Data to strobe hold time
Address to srobe setup time
Address to strobe hold time
RNW low to OP bus 3-state delay time
RNW high to OP bus 3-state delay time
RNW high to data valid delay time
tdis
ten
td(POW)
Output disable time
Output enable time
Delay time to power up
td(PD)
CIS Mode
Delay time to power down
td(LSD)
tw(ACYPW)
tw(ACLKH)
tw(ACLKL)
tsu(SMPSU)
td(OD)
CCD Mode
ACYC high to the first valid pixel delay time
ACYC pulse duration
ADCCLK high pulse duration
ADCCLK low pulse duration
Sampling setup time
ADCCLK to output data delay time
td(LSD)
tw(ACLKH)
tw(ACLKL)
tw(SRW)
tw(SVW)
td(ACLKSR)
td(SRSVN)
td(SRSVM)
td(OD)
ACYC high to the first valid pixel delay time
ADCCLK high pulse duration
ADCCLK low pulse duration
Sample Reset (SR) pulse duration
Sample Video (SV) pulse duration
ADCCLK low to SR low
Delay time SR low to SV high
Delay time SV low to SR high
ADCCLK to output data delay time
TEST CONDITIONS MIN TYP MAX UNIT
37.5
ns
37.5
ns
10
ns
10
ns
20
ns
50
ns
20
ns
50
ns
10
ns
10
ns
10
ns
10
ns
10
ns
0
ns
10
ns
10
ns
10
ns
2
ms
30
ns
1
µs
25
ns
125
ns
125
ns
20
ns
15
ns
1
µs
125
ns
125
ns
40
ns
40
ns
60
ns
20
ns
125
ns
15
ns
6
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