TLC8188 Datasheet, PDF (10/12 Pages) Texas Instruments – 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR

TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
PRINCIPLES OF OPERATION
color selection mode description
FME
0
0
0
1
1
1
MM1
0
0
1
0
0
1
MM0
0
1
0
0
1
0
NAME
Internal, no force mux
External, no force mux
Auto-cycling, no force mux
Internal, force mux
External, force mux
Auto-cycling, force mux
DESCRIPTION
Input mux, offset and gain register selected from internal register bits INTM1, INTM0
Input mux, offset and gain register selected from external pins MA1, MA0
MA1 MA0
0
0
Red
0
1
Green
1
0
Blue
Input mux, offset and gain register auto-cycled, R → G → B → R on ACYC pulse.
Input mux selected from internal register bits FM1, FM0; offset and gain register
selected from internal register bits INTM1, INTM0
Input mux selected from internal register bits FM1, FM0; offset and gain register
selected from external pins MA1, MA0
Input mux selected from internal register bits FM1, FM0; offset and gain register
auto-cycled, R → G → B → R on ACYC pulse
setup register 3 description
BIT
B1, B0
NAME
RCL1, RCL0
DEFAULT
No default setting
DESCRIPTION
These two bits control the input clamp voltage levels.
RCL1 RCL0
0
0 Clamp low, 1.5 V
0
1 Clamp high, 2.5 V
software reset description
BIT
B7–B0
Software reset, reset system to the default settings.
DESCRIPTION
auto-cycle reset description
BIT
B7–B0
DESCRIPTION
In auto-cycling mode this will reset auto-cycling to RED channel, RED gain register, and RED offset register.
read-only I.D. description
BIT
B7–B0
NAME
ID
DEFAULT
DESCRIPTION
Hard-coded device revision identification. This can be read in one of the test modes.
test register description
BIT
B5–B0
B7
B6
NAME
RA5–RA0
ST
RR
DEFAULT
00
0
0
DESCRIPTION
These six bits select the internal register to be read out at the output data bus.
Self test. 1 – self-test enable, the DAC output is connected to the PGA input. 0 – self-test disable (default)
Read internal register value from the output data bus. 1 – read enable, 0 – read disable (default). When
the RR bit is set to 1, the content of a register specified by RA5–RA0 can be read from the parallel data
bus upper 8 bits, OP(9–2). Both the parallel and serial ports can be used to write any internal registers,
but only the parallel port is used to read the registers.
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