TL16PNP100A Datasheet, PDF (6/20 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
switching characteristics
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN MAX UNIT
td1
Delay time, CS high to SCLK high
tSHCH
See Figure 8
50
ns
td2
Delay time, SIO input valid to SCLK high
tDVCH
100
See Figure 8 and Fig-
ns
tpd1
Propagation delay time, SCLK high to SIO level transi-
tion
tCHDX
ure 9
100
ns
tpd2
Propagation delay time, SCLK high to output valid
tpd3
Propagation delay time, SCLK low to CS transition
tCHQV
tCLSL
See Figure 9
500 ns
2
clock
period
td3
Delay time, CS low to D/Q output Hi-Z
tSLQZ
100 ns
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
tw1 Pulse duration, write strobe, IOW low
ALTERNATE
SYMBOL
TEST CONDITIONS
tWR
See Figure 5
tw2 Pulse duration, read strobe, IOR low
tw3 Pulse duration, master reset
tsu1 Setup time, data D7–D0 valid before IOW↑
th1
Hold time, chip select CSx valid after address
A0–A11 becomes invalid
th2 Hold time, data valid D7–D0 after IOW↑
td4 Delay time, CSx valid after address A0–A11 valid
th3 Hold time, address A0–A11 valid after IOW↑
td5 Delay time, IOR valid to data D0–D7 valid
td6 Delay time, IOR↑ to floating data D0–D7
td7
Delay time, INTR0↑, INTR1↑, INTR0↓, or INTR1↓
to IRQ↑ or IRQ↓
tRD
tMR
tDS
tCH
tDH
tCSRW
tAW
tCSVD
tHZ
See Figure 6
See Figure 5
From the first rising edge of XIN
after address becomes invalid,
See Figure 5 and Figure 6
See Figure 5
From the first rising edge of XIN
after address valid,
See Figure 5 and Figure 6
See Figure 5
CL = 45 pF after 2 clock periods,
See Figure 6
CL = 45 pF,
See Figure 6
See Figure 7
MIN MAX UNIT
2
clock
periods
3
clock
periods
1
µs
15
ns
20 ns
5
ns
30 ns
5
ns
30 ns
20 ns
15 ns
6
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265