TL16PNP100A Datasheet, PDF (5/20 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
MIN
4.75
2
– 0.5
0
NOM
5
MAX
5.25
VCC
0.8
70
UNIT
V
V
V
°C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP† MAX UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
Il
Input current
IOH = – 4 mA (see Note 1)
IOH = – 12 mA (see Note 2)
IOL = 4 mA (see Note 1)
IOL = 24 mA (see Note 2)
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other terminals
floating
VCC – 0.8
VCC – 0.8
V
0.5
V
0.5
± 1 µA
IOZ
High-impedance-state output cur-
rent
VCC = 5.25 V,
VSS = 0,
VO = 0 to 5.25 V,
Pullup transistors and pulldown transistors are off
± 10 µA
ICC
Supply current
VCC = 5.25 V,
All inputs at 0.8 V,
No load on outputs
TA = 25°C,
CLK at 4 MHz,
0.7 mA
Ci(CLK) Clock input capacitance
fCLK
Clock frequency
† _{All typical values are at VCC = 5 V and TA = 25°C.}
NOTES: 1. These parameters apply for all outputs except D7 – D0, IRQ3 – IRQ7 and IRQ9.
2. These parameters only apply for D7 – D0 and IRQ3 – IRQ7 and IRQ9 outputs.
15
20 pF
10
22 MHz
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN MAX UNIT
tw(SCLKH) Pulse duration, SCLK high to low (see Note 3)
tCHCL
250
ns
tw(SCLKL) Pulse duration, SCLK low to high (see Note 3)
tCLCH
See Figure 8
250
ns
fCLK
SCLK clock frequency (see Note 4)
0.3 0.68 MHz
NOTES: 3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles according
to the ST93C56 specification.
4. The SCLK signal is attained by internally dividing the frequency of the XIN signal by 32.
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