TL16PNP100A Datasheet, PDF (16/20 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
Table 6. PnP Logical Device Configuration Registers (continued)
ADDRESS PORT
VALUE
0×74
0×75
REGISTER NAME VALUE
DMA CHANNEL SELECT 0
This register has a value of 4 to indicate that DMA is not supported.
DMA CHANNEL SELECT 1
This register has a value of 4 to indicate that DMA is not supported.
READ/WRITE
CAPABILITY
Read only
Read only
POWER UP
00 00 01 00
00 00 01 00
EEPROM
The TL16PNP100A has been designed to interface with the ST93C56/66 EEPROM (SGS-Thomson) or an
equivalent. The EEPROM provides the block size for each device and the PnP resource data.
memory organization
The EEPROM should be organized as 128/255 words times 16 bits, so its ORG terminal should be connected
to V_CC or left unconnected. The EEPROM memory organization is shown in Table 7.
Table 7. EEPROM Memory Organization
EEPROM
BIT LOCATION
LOCATION _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
X 000
PnP Resource Data
X 128/255
EEPROM READ (see Figure 8 and Figure 9)
This device only supports read transactions. The READ op code instruction (10) must be sent to the EEPROM.
The op code is then followed by an 8-bit-long address for the 16-bit word. The READ op code with accompanying
address directs the EEPROM to output serial data on the EEPROM data terminals D and Q, which is connected
to the TL16PNP100A bidirectional serial data bus (SIO). Specifically, when a READ op code and address are
received, the instruction and address are decoded and the addressed EEPROM data is transferred into an
output shift register in the EEPROM. Each read transaction consists of a start bit, 2-bit op code (10), 8-bit
address, and 16-bit data. The TL16PNP100A does not accommodate the EEPROM autoaddress next-word
feature.
READ op code transfer (see Figure 8)
Initially, the EEPROM chip select signal (S) which connects to the TL16PNP100A EEPROM chip select (CS),
is raised. The EEPROM data, D and Q, then sample the TL16PNP100A SIO line on the following rising edges
of the TL16PNP100A serial clock, SCLK, until a 1 is sampled and decoded by the EEPROM as a start bit. The
TL16PNP100A SCLK signal connects to the EEPROM clock C. The READ op code (10) is then sampled on
the next two rising edges of SCLK. TL16PNP100A sources the op code at the falling edges of SCLK.
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