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THS1215 Datasheet, PDF (6/22 Pages) Texas Instruments – 3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH POWER DOWN
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THS1215
SLAS292A – MARCH 2001 – REVISED MARCH 2004
www.ti.com
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating conditions (AVDD = DVDD = 3.3 V, fs = 15 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, Tmin to Tmax) (unless otherwise noted)
REFT, REFB REFERENCE VOLTAGE (all supplies = 3.3 V)
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
INTERNAL REFERENCE(1)
VREFT Upper reference voltage
VREFB Lower reference voltage
VREF Differential reference voltage, VREFT – VREFB
Differential reference voltage, VREFT – VREFB accuracy
EXTERNAL REFERENCE
2.15
V
1.15
V
0.95
1 1.05
V
–5%
5%
Externally applied VREFT reference voltage range
Externally applied VREFB reference voltage range
Externally applied (VREFT – VREFB) reference voltage range
External mode VREFT to VREFB impedance
INTERNAL EXTERNAL REFERENCE
2
2.5
V
1.05
1.3
V
0.75
1.05
V
9
kΩ
CT
VREFT decoupling capacitor value
CB
VREFB decoupling capacitor value
CTB Decoupling capacitor VREFT to VREFB
DC ACCURACY (LINEARITY)
0.1
µF
0.1
µF
10
µF
Number of missing codes
All modes
0 codes
DNL Differential nonlinearity
All modes
±0.43 ±0.9 LSB
INL Integral nonlinearity
All modes
±0.6 ±2.5 LSB
Offset error
All modes
1.4
2.2 %FSR
Gain error
All modes
2.2
3.5 %FSR
DYNAMIC PERFORMANCE (all supplies = 3.3 V)
ENOB Effective number of bits
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINA Signal-to-noise + distortion
D
fi = 3.58 MHz
fi = 3.58 MHz
fi = 3.58 MHz
fi = 3.58 MHz
10.7 11.1
Bits
–81.2
dB
67.4 68.9
dB
66 68.6
dB
SFDR Spurious free dynamic range
Analog input bandwidth
fi = 3.58 MHz
72 81.7
180
dB
MHz
Differential phase, DP
0.12
degree
G(diff) Differential gain
TIMING (all supplies = 3.3 V)
0.01%
fCLK Clock frequency(2)
Clock duty cycle
5
45%
50%
15
55%
MHz
td(O)
td(PZ)
td(EN)
Output delay time
Delay time, output disable to Hi-Z output
Delay time, output enable to output valid
Latency
6
19
ns
3.2
ns
16
19
ns
4
5 cycles
(1) The internal reference voltage is not intended for use driving off chip.
(2) The clock frequency may be extended down to 5 MHz without degradation in specified performance.
6
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