TCA6424 Datasheet, PDF (6/29 Pages) Texas Instruments – LOW-VOLTAGE 24-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

TCA6424
LOW-VOLTAGE 24-BIT I²C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS175 – NOVEMBER 2007
www.ti.com
Data Output
by Transmitter
Data Output
by Receiver
NACK
ACK
SCL From
Master
S
Start
Condition
1
2
8
Figure 3. Acknowledgment on the I²C Bus
9
Clock Pulse for
Acknowledgment
BYTE
I²C slave address
I/O data bus
7 (MSB)
L
P07
P17
P27
Interface Definition
BIT
6
5
4
3
H
L
L
L
P06
P05
P04
P03
P16
P15
P14
P13
P26
P25
P24
P23
Device Address
The address of the TCA6424 is shown in Figure 4.
Slave Address
0
1
0
0
0
1
AD
DR
R/W
Fixed
Programmable
Figure 4. TCA6424 Address
2
1
0 (LSB)
H
ADDR
R/W
P02
P01
P00
P12
P11
P10
P22
P21
P20
ADDR
L
H
Address Reference
I²C BUS SLAVE ADDRESS
34 (decimal), 22 (hexadecimal)
35 (decimal), 23 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6424. Four bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register
can be written or read through the I²C bus. The command byte is sent only during a write transmission.
6
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