TCA6424 Datasheet, PDF (11/29 Pages) Texas Instruments – LOW-VOLTAGE 24-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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TCA6424
LOW-VOLTAGE 24-BIT I²C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS175 – NOVEMBER 2007
SCL
12 3 456 7 8 9
Slave Address
Command Byte
Data to Port 0
Data to Port 1
SDA S 0 1 0 0 0
1
AD
DR
0
A0
00
00
1 0/1 0/1 A 0.7
Data 0
Start Condition
Write to Port
R/W Acknowledge
From Slave
Acknowledge
From Slave
0.0 A 1.7
Data 1
Acknowledge
From Slave
1.0 A P
Data Out from Port 0
Data Out from Port 1
t_pv
Figure 6. Write to Output Port Register
Data Valid
t_pv
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SCL
1 2 34 56 78 9 12 34 56 7891234 56789 12 34 5
Slave Address
Command Byte
Data to Register
Data to Register
SDA
S
0
1
0
0
0
1
AD
DR
0
A
0
0
0
0
1 0/1 0/1 0/1 A MSB
Data 0
LSB A MSB
Data1
Start Condition
R/W Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Figure 7. Write to Configuration or Polarity Inversion Registers
LSB A P
Reads
The bus master first must send the TCA6424 address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6424 (see Figure 8 and Figure 9).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TCA6424
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